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SAT-Based Scalable Formal Verification Solutions

Part of the Series on Integrated Circuits and Systems Book Series

DOI: 10.1007/978-0-387-69167-1

ISBN: 978-0-387-69166-4

Publisher: Springer US - Springer Journals

Jan 1, 2007

1 - 10 of 13 Chapters

LitStream

Design Verification Challenges

Pages: 1 –16

[Verification ensures that the design meets the specification and has become an indispensable part of a product development cycle of a digital hardware design. Cost of chip failure is enormous due to high cost of respins and delayed tape-out, resulting in loss of opportunity to launch product on...
LitStream

Background

Pages: 17 –40

[Model checking is a method to verify whether a model obtained from hardware or software system satisfies a formal specification, written as temporal logic formulas such as Linear Time Logic (LTL) [87] or Computational Tree Logic (CTL) [88, 89].]
LitStream

Efficient Boolean Representation

Pages: 43 –62

[Many traditional tasks in computer-aided design such as equivalence or property checking, logic synthesis, static timing analysis, and automatic testpattern generation require an efficient representation of combinational circuits in terms of a network of Boolean primitives. Many practical...
LitStream

Hybrid DPLL-Style SAT Solver

Pages: 63 –76

[The Boolean Satisfiability (SAT) problem has extensive applications in VLSI CAD. Recent advances in SAT solvers based on Conjunctive Normal Form (CNF) representation have resulted in significantly improved performance. In particular, innovative techniques for decision variable selection [38],...
LitStream

SAT-Based Bounded Model Checking

Pages: 79 –112

[Bounded Model Checking (BMC) has been gaining ground as a falsification engine, mainly due to its improved scalability compared to other formal techniques. In BMC, the focus is on finding counterexamples (bugs) of a bounded length k. For a given design and correctness property, the problem is...
LitStream

Distributed SAT-Based BMC

Pages: 113 –129

[SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, is still computationally intensive, requiring large memory and time. Even with the many enhancements discussed in Chapter 5, sometimes the memory limitation of a single server, rather than time, can...
LitStream

Efficient Memory Modeling in BMC

Pages: 131 –153

[Designs with large embedded memories are quite common and have wide application. However, these embedded memories add further complexity to formal verification tasks due to an exponential increase in state space with each additional memory bit. In typical BMC approaches [45, 66, 109, 178], the...
LitStream

BMC for Multi-Clock Systems

Pages: 155 –171

[Current System-on-Chip (SoC) designs are essentially multi-clock systems with multiple clock domains, gated clocks, and latches. Further, the intellectual property (IP) blocks building SoC, with their own clock generators, mandate the requirement for synchronous primitives between the resulting...
LitStream

Proof by Induction

Pages: 175 –183

[Although BMC can find bugs in larger designs than BDD-based methods, the correctness of a property is guaranteed only for the analysis bound. However, one can augment BMC for performing proofs by induction [66, 67]. A completeness bound has been proposed [66, 67], to provide an inductive proof...
LitStream

Unbounded Model Checking

Pages: 185 –212

[SAT-based Bounded Model Checking (BMC) [45, 66, 109, 178] has been shown to be more robust and scalable compared to symbolic model checking methods based on Binary Decision Diagrams (BDDs) [12, 17]. Unlike BDD-based methods, BMC focuses on finding bugs of bounded length, successively increasing...

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