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Test Point Insertion for Multi-Cycle Power-On Self-Test

Test Point Insertion for Multi-Cycle Power-On Self-Test SENLING WANG* Graduate School of Science and Engineering, Ehime University, wang@cs.ehime-u.ac.jp XIHONG ZHOU Graduate School of Science and Engineering, Ehime University, g863003a@mails.cc.ehime-u.ac.jp YOSHINOBU HIGAMI Graduate School of Science and Engineering, Ehime University, higami@cs.ehime-u.ac.jp HIROSHI TAKAHASHI Graduate School of Science and Engineering, Ehime University, takahashi@cs.ehime-u.ac.jp HIROYUKI IWATA Renesas Electronics Corporation, hiroyuki.iwata.xg@renesas.com YOICHI MAEDA Renesas Electronics Corporation, yoichi.maeda.xd@renesas.com JUN MATSUSHIMA Renesas Electronics Corporation, jun.matsushima.vf@renesas.com Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST). Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method. CCS CONCEPTS • Integrated Circuits • Hardware Test • Design for testability Additional Keywords and Phrases: LBIST, POST, Multi-cycle Test, ISO26262, Functional Safety With the rapid evolution of technologies in developing automotive systems toward fully autonomous vehicles, various complex integrated circuits (ICs) are embedded in a car. The functional safety of the automotive system becomes a fundamental requirement as indexed by the ISO26262 standard [1]. Power-on Self-Test (POST) is the most common test solution to ensure the safety of a system. It tests the safety-critical components during the system’s startup before running any functional operations. It is thus helpful to detect any potential faults inside the components early to avoid a system failure. For testing automotive ICs, The POST needs to meet several constraints as follows. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the owner/author(s). © 2022 Copyright held by the owner/author(s). 1084-4309/2022/1-ART1 $15.00 http://dx.doi.org/10.1145/3563552 ACM Trans. Des. Autom. Electron. Syst.  Indispensable test quality: The ISO26262 standard imposes at least 90% latent fault metric to meet the most stringent automotive safety integrity level (ASIL D) for avoiding a random hardware failure (e.g., stuck-at faults) during the lifetime of ICs [1];  Limited test application time (TAT): test must be complete during the power-on reset at the engine startup (e.g., 10~50ms);  Low power: the consideration of power consumption during the test is helpful to avoid false tests under the delay fault model [2];  Low silicon overhead: suppress the increase of the Design for Test (DFT) hardware due to the ever-increasing complexity of ICs. In the past, many sophisticated solutions have been introduced to reduce the test volume of the standard LBIST, such as scan structure optimization [3, 4], the weighted random pattern [7, 8], random vector perturbing [9], Bit-flipping [10] and reseeding [11, 12, 13]. Test point insertion (TPI) technology improves the testability of CUT by inserting test logic into the CUT to deal with the detection of random pattern resistant (RPR) faults [14, 15, 16]. Other solutions focus on improving the test scheme of LBIST to enable the test-per-clock testing [17, 18], such as the shadow flip-flops insertion [19], and the Tri-Modal Scan test scheme [20] with reconfigurable scan cell design. Recently the deterministic test compression technology is also applied to the automotive ICs to run a POST or an in-system test [21, 37]. The deterministic compression test requires a modified BIST structure to allow applying the external test patterns generated by ATPG or continuous reseeding for high fault coverage. In this work, we focused on improving the test quality of an on-chip TPG-based LBIST by introducing a multi-cycle test described later to make the standard LBIST comply with the ISO26262 standard. Multi-cycle test applying more than one clock to run many times function operation after the scan -shift operation is a smart way to complement the quality of the test patterns (scan-in patterns) for test compaction [22, 23, 24], low-power testing [25, 26, 27], and logic diagnosis [28]. In a multi-cycle test, the response of CUT at each capture cycle is applied to the CUT in parallel as a capture pattern at the subsequent capture cycle. This feature is helpful to reduce the volume of scan-in patterns for attaining a target test coverage when the capture patterns can detect any additional faults that are missed by the root scan-in pattern. The multi-cycle test has the behavior to take the CUT closer to its functional operation conditions that can generate functional vectors with lower power consumption, which are very helpful to at-speed testing for delay fault detection [26, 27]. It is also easy to implement the multi-cycle test w/o the extra overhead in terms of software (e.g., modified ATPG for deterministic pattern generation) and hardware (e.g., reseeding logic & memory). Therefore, the multi-cycle test is expected to be a promising test scheme to a trade-off among the test coverage, TAT, silicon area, and low power for POST. A multi-cycle test may not always be effective for test reduction when the functional sequences generated by the CUT are not helpful to fault detection. Appropriate DFTs that can complement the value of the functional sequences are necessary to enhance the ability of the multi-cycle test to test reduction. Many DFT approaches to improve delay fault detection were presented in the past. In [29], the authors proposed a new scan cell named Transition-Launch Flip-Flop to complement the test vectors by modifying the value of partial FFs after the launch cycle in a two-cycle broadside test. In [30] and [31], the author expanded the approach of [29] to multi-cycle tests and proposed the DFT approaches to enhance the ability of the capture states to delay fault detection by holding [30] or reversing [31] the value of all FFs at the appropriate capture ACM Trans. Des. Autom. Electron. Syst. cycles. These DFT approaches considered the condition/requirement of the hard-to-detect delay faults in the multi-cycle test. In our previous works [32, 35], we have discussed the fault masking problem and the fault detection degradation problem (FDD) that would obstruct the effect of multi-cycle tests to detect stuck-at faults. It is necessary to solve the problems to reduce the test application time of POST under the indispensable test quality specified in the ISO26262 standard. The main difference between the existing DFT approaches and our works is to solve the Fault Masking and FDD problems for the stuck-at fault detection under the multi- cycle LBIST. The fault-masking problem denotes that the fault effects excited at the intermediate capture cycles might be masked before the effects are propagated to the final capture cycle for observation. To address this issue, we proposed a novel scan cell named the fault-detection-strengthened FF (FDS-FF) that directly observes and keeps the value of a faulty effect as it arrives at the FF during the capture operations [32, 33, 34]. The FDD denotes that the capability of capture patterns to detect additional stuck-at faults degrades with the increase of the number of capture cycles [35]. In [36], we have proposed a control point insertion (CPI) method to overcome the FDD by inserting control logic into scan FFs that modifies the value captured into the FFs during intermediate cycles, named the FF-CPI. While the basic idea is similar to the DFT proposed in [30, 31], our approach targeted controlling partial FFs but not the whole scan chain. We also proposed an approximate evaluation approach to identify CPs by analyzing the circuit structure without fault simulation. In general, the fault-simulation-based evaluation in [30, 31] needs more processing time than our method. Moreover, in this paper, we expand the FF-CPI approach of [36] to control the internal state of the combinational logic for stuck-at fault detection, which is different from the exiting DFT approaches will be described in Section 4. This paper consolidates the FDS-FF insertion approach denoted by OP (observation point) insertion and the FF-CPI approach into a complete DFT technique referred to as the test point insertion (TPI). Unlike the conventional TPIs which detect the random pattern resistant faults, our TPI focus on addressing the Fault Masking problem and FDD problem under a multi-cycle LBIST scheme to reduce the volume of scan-in patterns to meet the indispensable test quality specified by ISO26262. The main contributions of this paper are as follows. 1. We clarify the mechanism of Fault Masking and FDD by analyzing the stuck-at fault detection model in the multi- cycle BIST scheme. 2. We expand the FF-CPI approach to control the internal state of combinational logic by a newly proposed control logic circuit named Self-flipping CP to improve the testability for stuck-at fault detection under multi-cycle tests. 3. We propose a new metric to evaluate the effect of candidate signal lines for CP insertion under the multi-cycle BIST scheme. 4. We introduce an improved probabilistic cost function to estimate the effect of CP and OP insertion. 5. We introduce a consistent procedure to identify a user-specified number of CPs and OPs to achieve the most scan- in pattern reduction for attaining a target test coverage in the multi-cycle BIST scheme. ACM Trans. Des. Autom. Electron. Syst. 6. We evaluate the effectiveness of the proposed TPI for shortening the test application time based on the experimental results of ISCAS’89 and ITC’99 benchmark circuits under the single stuck-at fault model. The remainder of this paper is organized as follows. Section 2 introduces the basic concept of test -per- scan BIST, the multi-cycle test, and its issues. Section 3 describes the fault detection model under multi- cycle BIST. Section 4 presents the TPI approach for multi-cycle BIST. Section 5 shows the experimental results on benchmark circuits. Section 6 concludes the paper. 1 MULTI-CYCLE TEST SCHEME In this section, we first review the characteristic of scan BIST and multi-cycle BIST and discuss the problems of multi-cycle tests. 1.1 Scan BIST In a traditional test-per-scan BIST, pseudo-random vectors generated by the on-chip TPG are serially loaded into the scan chains driven by scan-shift clocks, known as scan operation. When all the scan registers are filled up, a complete scan-in pattern is latched to the inputs of the circuit. The circuit is then switched to the functional operation that generates the corresponding functional response at the outputs of the circuit. The FFs will be updated with the functional responses of the circuit when the trigger edge of the functional clock arrives, known as the capture operation. The captured functional response will be unloaded for fault detection as loading the next scan-in pattern. It is easy to observe that test is conducted only once by applying a complete scan-in pattern. Almost all test application time is consumed in the serial scan shift operation for test data delivery. 1.2 Multi-cycle BIST The multi-cycle test applies more than one functional clock to run many capture operations for every single scan-in pattern. In Figure 1, we show the operations during the multi-cycle test in the time-frame expansion of CUT. Let’s define a multi-cycle test by <s , v , c , o >, where s denotes a scan-in pattern; v denotes a i i ij i i i primary input vector; c denotes the responses of CUT captured into the scan chains represented by the ij capture patterns at the jth functional clock; o denotes a scan-out pattern which is the response of the combinational circuit when c is applied at the last capture. After a scan-in pattern s is loaded into the scan ij i chain in serial, the corresponding response c is generated at the outputs of combinational logic (FFs drawn in i1 dashed line) and captured into the FFs in parallel by the functional clock T1. Then, c is used as test stimuli i1 and latched to the circuit to generate a new response c , and c is applied and generate the corresponding i2 i2 response c in parallel until the final capture clock is applied. The response captured at the final capture o is i3 i unloaded for observation. It should be noted that the state of primary inputs v will be kept constant and the primary outputs in the intermediate capture cycle are considered unobservable during the capture operation. From Figure 1, it can be observed that conducting a multi-cycle test for each scan-in pattern <s , v > could i i provide more chances to detect additional faults through the functional capture patterns c . Therefore, it has ij promising potential to reduce the number of scan-in patterns for attaining a target test coverage that contributes to shortening the test application time due to fewer scan-shift operations. In addition, since the time of capture operation is negligible compared to the serial scan-shift operation, the reduction of the total test application time for POST is expectable. ACM Trans. Des. Autom. Electron. Syst. Primary outputs Primary inputs scan-in Combinational Combinational Combinational Combinational logic @T4 logic @T1 logic @T2 logic @T3 FF FF FF FF FF FF FF FF FF FF s o FF FF FF FF FF FF FF FF FF FF scan out c c c s i2 i3 i i1 i4 Latch clocks for s loading clocks for s loading and o unloading i T1 T2 T3 T4 i+1 i Scan shift clocks Multiple Functional Clocks M=4 Scan Enable Scan shift Mode Scan shift mode Capture Mode Figure 1. Test operations in multi-cycle BIST 1.3 The Problems of Multi-cycle BIST In our earlier works, we have raised two issues that would obstruct the effect of multi-cycle test to reduce the scan-in patterns for shortening the TAT of POST, called the Fault Masking [32, 33, 34] and Fault Detection Degradation of Capture Pattern [35, 36], respectively. The following gives a brief overview of these problems for this study. 1.3.1 Fault Masking Fault Masking denotes that the fault effects excited at the intermediate capture cycles by capture patterns might disappear before these effects are propagated to the final capture cycle for observation. Suppose that a fault f is excited at the first capture cycle by the scan-in pattern. To detect f, its faulty value has to be propagated through all M-1 capture cycles until the final capture cycle is applied. When the CUT has a deep combinational logic or the capture operation runs in a large cycle number, the time-expanded propagation path of the faulty value would become too long to be activated for detection, and the faulty value might be masked at certain logic due to the un-controllable logic state during the capture operation. Severe fault-masking would decrease the test quality of the scan-in patterns and capture patterns, and finally, obstruct the effect of the multi-cycle test for reducing the scan-in patterns. 1.3.2 Fault detection degradation problem (FDD) FDD means the capability of capture patterns to detect more additional stuck-at faults degrades as increasing the number of capture cycles. This is based on the observation that multi-cycle tests can take the CUT closer to its functional operation conditions with small internal transitions when increasing the capture cycles [26]. The functional operation would consequently cause the states of the large number of FFs to become constant when a number of capture cycles are applied. Since the value of FFs is reused as test stimuli at the ACM Trans. Des. Autom. Electron. Syst. subsequent capture cycles, the large number of FFs with constant values would cause the loss of randomness property of the capture patterns that obstructs the detection of additional faults. 2 FAULT DETECTION MODEL IN MULTI-CYCLE BIST In this section, we give a detailed analysis of the stuck-at fault detection model in a multi-cycle BIST scheme to elucidate the mechanism of Fault Masking and FDD as follows. For a stuck-at fault F , its faulty effect will always exist at each capture cycle during the capture operation, and we express it by f in the time-expanded circuit as shown in Figure 2. The faulty effect of F at each ij i capture cycle might be excited by the inputs of CUT. We use Pe to denote the probability to excite fault F ij i at the jth capture cycle. To detect F , the excited faulty value of F at the jth capture cycle (f ) must be i i ij propagated to the scan FFs for observing after the final capture, and we denote the propagation probability as Pp . ij In LBIST, Pe and Pp of a stuck-at fault F can be estimated by computing the controllability ij ij i/s ( ) and the observability ( ) of signal line i through the probabilistic random pattern testability measure such as COP (Controllability Observability Procedure). Hence, the detection probability of F at i/s the jth capture cycle denoted by Pd can be expressed by Pd = × . For a multi-cycle test with M ij/s ij/s capture cycles, the fault F would have M times opportunity to be excited by the capture patterns c ~c , i/s i1 iM and F will be detected out of once the fault is excited and propagated to the outputs. Hence, the detection i/s probability of F denoted by Pd in a multi-cycle test is the complementary probability of the case that F i/s i/s i/s cannot be excited and propagated for detection at all capture cycles, which can be expressed by: ∏ (1) Primary Primary outputs inputs scan-in Combinational Combinational Combinational Combinational logic @T4 logic @T1 logic @T2 logic @T3 FF FF FF FF FF f f f i1 i2 i3 f FF FF FF FF FF i4 × × × i i × Fi FF FF FF FF FF FF FF FF FF FF Pe i1 scan c c c c i2 s i1 i3 i4 out Pd = Pe *Pp Pd = Pe *Pp Pd = Pe *Pp Pd = Pe *Pp i1 i1 i1 i2 i2 i2 i3 i3 i3 i4 i4 i4 : Fault excitation : Faulty value propagation Figure 2. Single stuck-at fault detection in time-expanded circuit To calculate the controllability and the observability of signal lines at each capture cycle, we transform the CUT to M cycles time-frame expansion combinational circuit. We initialize the 0/1 controllability ( and ) of PI (primary input) and PPI (pseudo-primary input: FF) at the first capture cycle to 0.5/0.5, then, calculate the value of and for each gate at each time-frame. The observability of signal line at each ACM Trans. Des. Autom. Electron. Syst. time-frame is calculated starting from the PO (primary output) and PPO (pseudo-primary output) at the last capture cycle with initial value of 1.0, tracing back to the PI and PPI until the first capture cycle. Compared to the traditional scan test with a single capture, the multi-cycle test shows the potential to improve the probability of fault detection for every single scan-in pattern followed by multiple capture patterns. However, the fault detection in the multi-cycle test depends on the controllability and observability of signal lines in the time-expanded circuit, which is generally deteriorating as increasing the number of capture cycles. For demonstration, we conducted preliminary experiments on ISCAS89 and ITC99 benchmark circuits to evaluate the average 1-controllability and the observability of signal lines at each capture cycle. Figure 3 shows the results. In Figure 3. a, it can be observed that ITC99 circuits show higher 1-controllability, which implies the internal states of these circuits are easy to be 1, whereas ISCAS89 circuits likely trend to b e 0. Figure 3. b shows the standard deviation of 1-controllability of signal lines at each capture cycle corresponding to the results of Figure 3. a, to demonstrate the impact of increasing capture cycles on the controllability. The results show that the standard deviation of 1-controllability becomes higher as increasing the capture cycles, which implies the controllability of more signal lines is biasing toward either 0 or 1; in other words, the value of more signal lines in a large capture cycle would be most likely fixed at 0 or 1 during the tests. For a signal line with stuck-at fault, higher 0-controllability (0-bias) is helpful to excite the s-1 fault, whereas exciting the s-0 fault becomes difficult. Moreover, the biased controllability of signal lines in a time frame would also affect the path sensitization for propagating the excited faulty values to the FFs in the current time frame. We insist on it as the root cause of FDD observed in our previous works. ACM Trans. Des. Autom. Electron. Syst. s9234 s13207 s38584 b11 b12 b14 b15 b20 s9234 s13207 s38584 b11 b12 b14 b15 b20 0.38 0.75 0.36 0.7 0.34 0.65 0.32 0.6 0.3 0.55 0.5 0.28 0.45 0.26 0.4 0.24 0.35 0.22 0.3 0.2 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Capture Cycle Number Capture Cycle Number a. Average one-controllability of signal lines at each capture cycle b. Standard Deviation of one-controllability results at each capture cycle s9234 s13207 s38584 b11 b12 b14 b15 b20 s9234 s13207 s38584 b11 b12 b14 b15 b20 0.7 0.5 0.45 0.6 0.4 0.5 0.35 0.4 0.3 0.3 0.25 0.2 0.2 0.15 0.1 0.1 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Capture Cycle Number Capture Cycle Number d. Standard Deviation of Observability results at each capture cycle c. Average Observability of signal lines at each capture cycle Figure 3. Testability vs. Capture Cycles Regarding the observability shown in Figure 3.c and 3.d, it can be observed that in a 10-times expand circuit the value of more signal lines in earlier capture cycles is more difficult to be observed from the outputs (scan FFs) after the final capture. The deterioration of observability of signal lines at early capture cycles causes the faults excited at an early capture cycle difficult to be propagated to the final capture cycle for detection, which is the root cause of the fault masking. Based on the above analysis, we derive that the primary factor affecting the multi-cycle test to reduce the scan-in patterns for shortening the TAT of POST should be the incompatibility between the controllability and observability in the time-expanded circuit under multiple capture cycles. Where smaller 0/1 controllability bias of signal line at earlier capture cycles with lower observability. We insist that reconciling the incompatibility of testability under the multi-cycle test is necessary to improve the performance of multi-cycle BIST for scan-in pattern reduction. 3 TEST POINTS FOR MULTI-CYCLE BIST In this section, we introduce the observation point and control point proposed in our previous works [32, 33, 34, 35, 36] to address the Fault Masking and the FDD of the multi-cycle test, respectively. ACM Trans. Des. Autom. Electron. Syst. Observability 1-Controllability Standard Deviation of Observability Standard Deviation of 1-Controllability Port Function Shift Mode Capture Mode User Mode DATA FDS-FF DATA Data In don’t care 0/1 0/1 SEN SIN Scan-in 0/1 0/1 don’t care SEN Scan Enable 1 0 0 SIN Q CLK Clock 010 010 010 FF SEQ_TEST_EN Sequential 1 1 0 SEQ_TEST_EN Test Enable CLK Status !SIN DATA^!SIN DATA a. logic design of FDS-FF b. Operation mode of FDS-FF CLK Normal Scan Chain SFF SFF SFF SFF SFF CUT FDS-FF FDS-FF FDS-FF FDS-FF FDS-FF SEN FDS Scan Chain SEQ_TEST_EN CLK c. LBIST with an independent FDS-FFs scan chain Figure 4. The DFT architecture of FDS-FF insertion for LBIST. 3.1 Observation Point: FDS-FF To improve the observability of scan FFs at the intermediate capture cycles in the time-expanded circuit, we proposed a new scan-cell design named fault-detection-strengthened FF (FDS-FF) that can directly observe and keep the value of FFs captured at each cycle. Figure 4 shows the structure of FDS-FF and the DFT architecture for LBIST with FDS-FF insertion. The output of CUT denoted as DATA is controlled by scan enable signal (SEN) through a NOR gate, and a sequential test controls the scan-in test enable signal (SEQ_TEST_EN) through a NAND gate. The FDS-FF can work in three modes: Shift, Capture, and User mode as shown in the table, where Shift and Capture modes refer to as the Test mode, and User Mode refer to as the functional operation. The CUT will work at the user mode when SEQ_TEST_EN and SEN are set to 0. In Test Mode, SEQ_TEST_EN is set to 1, and the SEN signal controls the shift and the capture modes. If SEN=1, the test pattern is loaded into FF. If SEN=0, the corresponding test responses are captured. It should note that the test responses of CUT captured at each cycle are XORed with the SIN, which is the data stored in the neighbor FF in the scan chain. In this way, the test responses of each cycle can be compacted by the XOR gate, and the compacted test responses will be applied to the next capture cycle as a new test pattern. Since FDS-FFs observe and keep the capture response of CUT during the capture operation, in order to avoid functional timing issues, all FDS-FFs are extracted to constructed into a daisy chain and isolated from the other normal scan chains. ACM Trans. Des. Autom. Electron. Syst. LFSR Phase shifter MISR PI PO SI lost FF FF FF Excited 1 FF Fault FF FF FF FF FDS- FDS FDS FDS 0 lost FF FF FF FF lost FF FF FF FF SO Observe & Keep the faulty value before vanishing Figure 5. Replace a scan-FF with FDS-FF to address fault masking Figure 5 shows the effect of FDS-FF to address the fault masking problem. In a time-expanded circuit, some faulty values are successfully propagated to the FF at the intermediate capture cycles, however, would be masked before the final capture. Replacing a scan FF with the FDS-FF is equivalent to inserting an observation point into the time-expanded circuit to observe and keep these faulty values before they are masked. However, it is impractical to replace all scan-FFs with FDS-FFs, the fault effects that never pass through the selected FDS-FFs may disappear if they cannot be propagated to the final capture cycle. Fortunately, replacing a small count of scan cells with FDS-FFs could achieve significant fault detection improvement [33], which is beneficial for low hardware overhead. 3.2 Control Point: Self-Flipping CP Insert control points into the circuit to force the target signal line to 0 (0-control) or 1 (1-control) is a popular way to improve the testability of the circuit. However, it would be challenging to adapt the conventional CPI to the time-expanded circuit under multi-cycle BIST because 1) CP with a fixed control value during a complete capture operation is less helpful to relax the controllability biasing; 2) generating the control values for each capture cycle requires complex sequential ATPG; 3) applying the dynamic control value to CP during the capture operation requires intricately designed control logic. In [35, 36], we have proposed an FF-CPI approach to improve the controllability of the time-expanded circuit by modifying the captured values of partial scan FFs at each capture cycle. The FF-CP compares the state of FF at the current capture cycle with its state at the previous capture cycle and changes the current state to its inverse value if no state transition occurs on the FFs during the capture cycles. In this paper, we expand the FF-CPI approach to control the combinational logic and propose the control logic that can flip the value of the signal line of CP during the capture operation. We call it the Self-Flipping control in this paper described as follows. Figure 6 shows the design of the Self-Flipping control logic. In the capture mode, the present state (CP_OUT@T : the state of CP after the previous capture cycle) and the new state (CP_IN@T : the input i-1 i value of the candidate CP of the current capture cycle) of the CP are checked whether there is a transition occurs in the current capture cycle or not. If not, the Self-Flipping control logic will generate the inverse value of the input state to the CP output (CP_OUT@T ). An external control signal “CAP_CTR” is used to ACM Trans. Des. Autom. Electron. Syst. enable the self-Flipping when set to 1. Otherwise, the input value of CP passes through the CP logic to the output. It thus can keep the value of a target signal line at the adjacent time-frame always different to relax the bias of 0/1-controllability caused by successive capture cycles. Combinational Logic @Ti Combinational Logic @Ti-1 Scan-out FF FF FF FF FF FF CP_IN CP_OUT Candidate FF FF FF CP Scan-in a. inserting a self-flipping control point into the time-expanded circuit CP_OUT CP_IN CP_OUT CP_OUT CAP_CTR CP_IN @Ti-1 @Ti @Ti 1 0 0 1 1 0 1 1 1 1 0 0 FF 1 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 Capture clock CAP_CTR 0 1 1 1 b. self-flipping control logic c. The truth table of self-flipping control logic Figure 6. Self-Flipping CP insertion for multi-cycle LBIST It is worth noting that a traditional inversion CP using an XOR gate would be ineffective in reducing the 0/1-controllability bias because the 0/1-controllability of XOR-CP output depends on the input signal line, which is biasing as increasing the capture cycles. While inserting the Self-Flipping CP will cause hardware increase, it operates automatically during the capture cycles w/o any external control, which does not cause the extra cost in updating the ATPG to generate the control vectors. To implement the proposed multi-cycle LBIST scheme for POST, the unknown values (Xs) generated as switching the operation mode from test and function need to be dealt with carefully. This issue can be addressed by separating the control logic of POST from the test target of POST (CUTs) through wrapper logic. During the test operation, the wrapped control logic of POST will be kept in function mode. When the test is completed, the CUTs will be switched to the functional mode by a system reset through the control logic of POST. The detailed solutions to handle the implementation issues for in-system-testing have been introduced in [37, 38]. ACM Trans. Des. Autom. Electron. Syst. 4 TP SELECTION FOR MULTI-CYCLE BIST This section introduces the procedure to determine the locations of CPs and OPs to address the Fault Masking and the FDD problem induced by the controllability biasing and observation deterioration under a multi-cycle LBIST scheme. While the selection procedure inherits some underlying techniques proposed in our previous works, such as the structure-based evaluation metric and the probabilistic testability analysis of circuits for FDS-FFs and FF-CP insertion, in this paper, we consolidate them into a consistent process for TP selection under multi - cycle BIST through the following efforts:  We propose a new metric to evaluate the effect of candidate signal lines for CP insertion under a multi-cycle BIST scheme.  We introduce an improved probabilistic cost function for estimating the effect of candidate TPs.  We introduce an OP Pruning approach into the TP procedure to improve the efficiency of TP selection under the multi-cycle BIST scheme. It is worth noting that the proposed TP selection procedure conducts the probabilistic evaluation to identify the candidate CPs and Ops. The proposed TP selection procedure is a time-saving process because it does not use the conventional fault simulation. As a result, we obtain the list of the TPs, then we evaluate the fault coverage achieved under the circuit with TPs by conducting the multi-cycle test fault simulation at one time. 4.1 A new Evaluation Metrics for CP selection As discussed in Section 3, increasing the number of capture cycles would cause a significant 0/1 - controllability bias on signal lines at later capture cycles, which implies the value of more signal lines in a large capture cycle would most likely fix at 0 or 1 in most capture cycle. For a signal line x, if setting its value to 0(1) would cause fewer gates with fixed output value in its arrival logic region to FFs than that of setting to 1(0), 0(1)-controllability bias of x due to the multiple capture cycles would be helpful to fault excitation and propagation we call it positive bias, 1(0)-controllability bias would obstruct the fault detection called the negative bias. For the signal line shows a negative bias in controllability, it is suggested to insert a self-flipping CP to relax its controllability bias in the multi-cycle test. Following this, we propose the method to calculate the degree of the 0/1 controllability bias when inserting a CP into the signal line.  x: a signal line in the combinational circuit  p : the probability of line x’s value being logic 0 x/0  p : the probability of line x’s value being logic 1, where, p +p =1.0 x/1 x/1 x/0  fg : the number of gates in the arrival logic region from line x to POs/PPOs whose output value will be fixed, x/0 as setting the value of x to 0  fg : the number of gates in the arrival logic region from line x to POs/PPOs whose output value will be fixed x/1 by setting the value of x to 1  BD(x): the degree of controllability bias at line x that would impact the fault detection, where BD(x)>0 denotes a positive bias, BD(x)<0 denotes a negative bias. BD(x)=(p -p )×(fg -fg ) (2) x/0 x/1 x/1 x/0  CD(x): the degree of contribution to relax the controllability bias as forcing the 0/1-controllability of line x to 0.5/0.5. CD(x)>0 denotes a positive contribution, CD(x)<0 denotes a negative contribution that would be achieved by CP insertion. ACM Trans. Des. Autom. Electron. Syst. CD(x)=(p -0.5)×fg +(p -0.5)×fg =(0.5-p )×(fg -fg ) (3) x/0 x/0 x/1 x/1 x/0 x/1 x/0 We use the s27 circuit as an example for illustration, see Figure 7. For signal line i, two paths connect with the PPO (FF2) through path 1: i → G5 → G7 → G8 → w, and path 2: i → G6 → G7 → G8 → w. When the value of i is 1, the output of G5, G6, and G7 will be fixed at 1, 1, 0, respectively, thus fg =3. i/1 When i is 0, the output of G5 and G6 depends on the other input signal lines n and c, which implies a 0 value at i cannot directly cause any fixed gates on the two paths to FFs, thus fg =0. The probability of signal i/0 line i’s values p and p can be calculated using the COP measurement, which is 0.25 and 0.75. The degree i/1 i/0 of controllability bias is hereby BD(i) = 0.5×3 = 1.5, which represents that the controllability bias at signal line i is positive to fault detection. For the signal line with positive controllability bias, inserting a CP would cause more fixed gates on the fault propagation paths to FFs with a negative contribution to fault detection, e.g., CD(i)=-0.25×3=-0.75. Table 1 gives the evaluation value of some signal lines shown in Figure 7. It can be observed that signal lines q and s show the negative controllability bias in BIST, and inserting a CP to s would achieve the most contribution to fault detection. Figure 7. The combinational logic frame of s27 circuit Table 1: evaluation metrics of signal lines in s27 line # fg fg p p BD CD x/0 x/1 x/0 x/1 h 0 2 0.75 0.25 1 -0.5 i 0 3 0.75 0.25 1.5 -0.75 n 0 1 0.75 0.25 0.5 -0.25 q 3 0 0.56 0.44 -0.36 0.18 s 0 2 0.27 0.73 -0.92 0.46 As shown in Figure 3, the controllability bias on signal line changes at different capture cycles in the multi-cycle BIST. It becomes larger as increase the number of capture cycles. Thus, the degree of ACM Trans. Des. Autom. Electron. Syst. controllability bias of signal line x: BD(x) and the contribution of CP insertion to relax the impact of controllability bias on fault detection: CD(x) can be easily extended for the multi-cycle test as follows. ∑ (4) (5) where p and p denote the probability of line x’s value being logic 1/0 at the jth capture cycle. We use CD as the xj/1 xj/0 evaluation metrics for searching the candidate signal lines for CP insertion under multi-cycle BIST, which is described in the next section. 4.2 TP Selection Procedure for Multi-cycle BIST The procedure consists of two phases, Phase 1: CP insertion under a time-expanded circuit with full FF- observation, and Phase 2: OP is pruning to remove the impotent observation points (FDS-FF). In Phase 1, the CP selection will be performed at the time-expanded circuit with full observation where the FFs at intermediate capture cycles are supposed to be observable. This is because the purpose of self- flipping CP insertion is to relax the controllability bias caused by functional operation at each time frame, but not to create long propagation paths that can cross multiple time frames to the final capture cycle for observation which is an arduous task. The algorithm for CP insertion is shown in Algorithm 1. To evaluate the quality of CPs and OPs, cost function U as follows is widely used in various TPI techniques. (6) In this work, we expand the cost function considering the fault detection model under the multi-cycle BIST scheme, where the detection probability of the faults at a signal line denoted by Pd is calculated by x/s ∏ (7) C and O denote the s-controllability and observability of signal line x at the jth time-frame, respectively, computed by xj/s xj org tp COP measure as discussed in Section 3. The difference in U before (U ) and after (U ) inserting a TP can be calculated by the following equation to identify the most effective TP from a candidate TP list. (8) In Phase 2, we will remove the impotent observation points from the time-expanded circuit to reduce the hardware overhead caused by FDS-FFs insertion, named OP pruning, as shown by Algorithm 2. In OP pruning, the input is the time-expanded circuit with CP insertion achieved at Phase 1 where all scan FFs are replaced with FDS-FFs for observation during multi-cycle captures. We target on reducing the amount of FDS-FFs to a user-specified number N by restoring the FDS-FFs that do not affect the fault detection to op ACM Trans. Des. Autom. Electron. Syst. scan FFs. As shown from line 14 to line 24 of algorithm 2, we compute the cost U of each candidate FDS-FF when temporarily changing it to a scan FF which is equivalent to a wire in the intermediate time-frame circuit, and remove the one which has the least cost increase from the OP list. The OP pruning is considered effective based on the following observations. 1) The large number of signal lines usually can be observed by multiple FFs; 2) The FFs which have larger observable logic regions could observe more fault effects. 3) The number of FFs in a design is much smaller than that of signal lines, and exploring the inactive FFs would be more time-saving than inserting OPs into the CUT. ALGORITHM 1: CP insertion Inputs: net: original CUT netlist M: the number of capture cycles N : Maximum number of CPs cp Outputs: cplist[N ]: Selected CP list cp net : CUT with CP insertion cp Optional parameter: CR : the threshold of cost reduction (≥0) threshold N : number of candidate CP at each iteration of CP decision cand Process: 1: cplist ← 2: cand ← /*Candidate CP list for determining a CP*/ 3: read_circuit (net); 4: fix_gate_cal(net); /*computing fg , fg */ x/0 x/1 5: time_expansion (net, M); 6: full_observation_point_insertion( ); 7: while |cplist|< N do cp 8: cop_controllability(net ); cp 9: cop_observability(net ); cp 10: CD_calculate (net ); cp 11: cand ← ; 12: for j=1 to # of available candidate CP do 13: cand[j] ←unchecked signal line with the largest CD; 14: end for 15: if cand= then 16: return cplist, net ; stop the process cp 17: else org 18: U =cost_computation(net ,M); cp 19: for k=1 to N do cand 20: net =insert cand[k] cp to net ; cp cp 21: update_controllablity_observability(net , M); cand[k] org 22: =U -cost_computation(net , M); cp 23: Remove cand[k] from net ; cp 24: end for 25: If maximum( )>= CR then k threshold ACM Trans. Des. Autom. Electron. Syst. 26: cplist[i]←cand[k]; 27: end if 28: end if 29: insert cplist[i] to net → update net ; cp 30: end while 31: return cplist, net ; cp end process ALGORITHM 2: OP Pruning Inputs: net : CUT with CP insertion cplist M: number of capture cycles N :Target number of OPs (FDS-FFs) op Outputs: oplist[N ]: FF list for FDS-FFs insertion op net : CUT with TPs (CP and OP) tp Optional parameter: N : # of candidate OPs at each iteration for OP pruning cand Process: 1: oplist ← 2: cand ← /* Candidate target OP list for pruning */ 3: read_circuit (net ); cp 4: oplist← all FFs 5: structure_analysis(net ); cp 6: FF_ranking(oplist) /*Ranking the FFs by the approximate evaluation metrics proposed in [39]*/ 7: while |oplist|>N do op 8: for j=1 to # of available candidate OP do 9: cand[j] ←select an OP in the oplist in descending order which is unchecked; 10: end for 11: if cand= then 12: return oplist, net ; stop the process tp 13: else org 14: U =cost_computation(net ,M); tp 15: for k=1 to N do cand 16: remove cand[k] OP from net ; tp 17: update_observability(net ); tp org 18: =U -cost_computation(net , M); tp 19: restore cand[k] OP to net ; tp 20: end for 21: If =minimum then 22: remove cand[k] OP from net ; tp 23: remove cand[k] from oplist; 24: end if 25: end if 26: end while 27: return oplist, net ; tp end process ACM Trans. Des. Autom. Electron. Syst. 5 EXPERIMENTAL RESULTS Experiments are conducted on ISCAS89 and ITC99 benchmark circuits to evaluate the effect of TPI under 16 15 13 4 multi-cycle BIST. A 16-bits internal type LFSR (characteristic polynomial: X +X +X +X +1) with Phase Shifter generates pseudo-random patterns. A parallel scan structure is introduced into the CUT that consists of multiple scan chains up to 100 FFs in length (when the total number of FFs > 1600, the maximum length of the chain is up to 200). A multi-cycle BIST logic/fault simulator that can simulate at most 50 cycles capture per pattern is implemented in-house for stuck-at faults testing. For automotive ICs, the ISO26262 functional safety standard imposes at least 90% latent fault metric (permanent fault) to meet the safety goal ASIL D. Therefore, in this study, we set a target fault coverage 90% and evaluate the effect of the proposed multi-cycle TPI that would make the classical on-chip pseudo-random TPG-based LBIST comply with the ISO26262 standard. Table 2 gives the details of CUTs. Table 2: Detailed information of benchmark circuits # of N N #OPs (FDS-FFs) cp cp Circuit # gate # FF stuck-at fault (<1% of gates) (<5% of FFs) (<20% of FFs) s9234 5597 228 6927 55 11 45 s13207 7951 669 9815 79 33 133 s15850 9772 597 11725 104 29 120 s38417 22179 1636 31180 1141 85 327 s38584 19253 1452 36303 97 72 290 b11 437 31 1322 2 1 6 b12 904 121 2797 9 6 24 b14 4444 245 12811 44 12 49 b15 8338 449 23528 8 8 89 b17 22645 1415 65464 201 70 283 b20 8875 490 25338 88 24 98 5.1 Evaluation of the efficiency of the multi-cycle test We first performed fault simulations on the regular scan testing with single capture (SCAN) and multi-cycle testing with 2, 4, 6, 8, and 10 capture cycles, respectively, to evaluate the effect of multi-cycle testing for fault detection, using 100k test patterns (scan-in) generated by LFSR. Figure 8 shows the fault coverage of each circuit at different capture cycles when 100k patterns are applied. It can be seen that for most circuits, the multi-cycle test achieved an increase in fault coverage at the 2 and 4 capture cycles. As continuously increasing the capture number to 10 cycles, the increment of fault coverage is slowing down or getting degraded. For s9234, the multi-cycle test shows a significant decrease in fault coverage. It can be explained by the incompatibility of testability shown in Figure 3, where the 10-cycle test caused a little controllability bias, however, significant deterioration of the observability in the expanded circuit. ACM Trans. Des. Autom. Electron. Syst. scan 2-cycle 4-cycle 6-cycle 8-cycle 10-cycle s9234 s13207 s15850 s38417 s38584 b11 b12 b14 b15 b17 b20 Figure 8: fault coverage of benchmark circuit with 100k patterns Effect of multi-cycle test on the fault detection of benchmark circuits SCAN 2cycles 4cycles 6cycles 8cycles 10cycles # of scan-in patterns Figure 9: scan testing vs multi-cycle testing Figure 9 shows the curve of the average fault coverage of all CUTs by increasing the number of patterns. The horizontal and vertical axis shows the pattern number and the corresponding fault coverage, respectively. The average fault coverage of all CUTs confirms that the multi-cycle test has a statistical improvement in fault detection for most benchmark circuits compared with scan testing (SCAN). Applyi ng 4 ACM Trans. Des. Autom. Electron. Syst. Fault Coverage(% ) Fault Coverage (%) 98535 and 6 capture cycles achieved the most fault coverage improvement, and the increment of fault coverage becomes less as the number of capture cycles increases to 8 and 10 cycles. The above observations fit the basic feature of multi-cycle testing discussed in Section 3. Multiple capture operations would provide more detection opportunities for the fault that the scan-in pattern cannot detect. Therefore, it is possible to improve the fault detection of the scan-in pattern. However, the deterioration of testability of signal lines in the time-expanded circuit would interfere with future fault detection as increasing the capture cycles. To reinforce the effect of multi-cycle BIST on scan-in pattern reduction, CP insertion and FDS-FFs insertion are introduced, and their effects are described as follows. 5.2 Evaluation of the efficiency of the CPI and the OPI We conducted the CP selecting and OP pruning algorithm proposed in Section 5 on the benchmark circuits to identify a specified amount of CPs and FDS-FFs, where the maximum number of CPs N was set to 1% of cp the gate number of CUT, and 5% of the FFs, respectively. The expected amount of FDS-FFs is set to 20% of the total number of FFs in the CUT. The number of CPs and FDS-FFs are shown in the fifth and the sixth column of Table 2, respectively. To demonstrate the difference between OPI and CPI, we performed fault simulation under 10 cycles by individually inserting the identified CPs and OPs into the CUTs, denoted by CP-ONLY and OP-ONLY, respectively. CPI&OPI denotes inserting both the CPs and OPs into the CUTs. Figure 10 shows the curve of average fault coverage of the benchmark circuits, increasing scan-in patterns to 100K under different DFT strategies. The figure only presents the curves up to 50K patterns for demonstration. Full observation replaces all FF with FDS-FFs has been conducted on the CUTs w/(w/o) CP insertion denoted by FullOB, CP&FullOB, respectively. While it is not for practical use due to hardware overhead concerns, the results represent the upper bound of the fault coverage possibly achieved by OPI, which is used to evaluate how far the OP pruning has reached in identifying the OPs for FDS-FFs insertion. ≒24.4X reduction 585 by CPI&OPI 14260 scan-in patterns by 10-Cycle Test to gain 90% fault coverage 2195 by CPI_ONLY 5175 by OPI_ONLY + + + SCAN 10-Cycle OPI_ONLY FullOB CPI-ONLY CPI&OPI CP&FullOB Number of Scan-in Patterns Figure 10: Fault coverage vs. Pattern number (scan testing, multi-cycle testing, OPI and CPI under multi-cycle testing). ACM Trans. Des. Autom. Electron. Syst. Fault Coverage (%) 49585 Compared to the regular scan test (SCAN), the multi-cycle test w/o TPI denoted by “10-Cycle” in the figure achieved a significant fault coverage improvement where a target fault coverage (90%) is attained by applying 14,260 scan-in patterns under a 10-cycle test, which cannot be achieved by scan testing even with more than 100K scan-in patterns. Replacing 20% of FFs with FDS-FFs (OPI-ONLY) further improved the fault coverage and reduced the necessary scan-in patterns to 5,175 for the target 90% fault coverage as well as the effect achieved by full observation (replacing all scan FFs with FDS-FFs). The results demonstrate the effect of FDS-FFs insertion that directly observes the values of FFs at each capture cycle to relax the fault masking problem in the time-expanded circuit. Note the fault coverage curve of CPI-ONLY in Figure 10, where we inserted 1% of the gate number of CPs into the CUTs, and it shows almost the same fault coverage improvement (≈93%) and much more scan- in pattern reduction (2,195 for 90% fault coverage) than that of OPI-ONLY. The results indicate 1) inserting Self-Flipping CP into the CUT that relaxes the controllability bias in a time-expanded circuit is helpful in improving the fault detection of capture patterns 2) the effect of CPI is limited due to the fault masking problem in the time-expanded circuit. When inserting both the identified CPs and OPs into the CUTs denoted by CPI&OPI, we achieved a sharp increase in fault coverage compared to inserting CPs and OPs individually. The final fault coverage of 100K scan-in patterns increases to 95.01%. The number of scan-in patterns for achieving 90% fault coverage is drastically reduced to 585 (24.4X reduction compared to the multi-cycle test). Note the fault coverage curve of 10-cycle (multi-cycle test) and the CP&FullOB, which represents the upper bound of the fault coverage possibly achieved by CPI&OPI, inserting both the CPs and OPs (CPI&OPI) identified by our proposed method achieved remarkable fault coverage increase and pattern reduction that is very close to the upper bound. Table 3 and Table 4 show the detailed results of the final fault coverage achieved by applying 100K patterns and the number of scan-in patterns for attaining 90% stuck-at fault coverage, respectively. The experimental results when inserting fewer CPs (<5% of FFs) into the benchmark circuits are also presented in the tables. The results show that the 10-cycle test would cause the fault coverage loss in most ISCAS89 circuits (s9234, s13207, s38584); however, it achieves a significant increase in ITC99 benchmark circuits. Where ISCAS89 circuits show a much more testability bias, increasing the capture cycles are vulnerable to fault masking and FDD problem. While inserting OP or CP individually both improved the fault coverage and reduce the patterns for attaining 90% fault coverage for all circuits, it suggests that combining the CPs and OPs can achieve the most pattern reduction under the multi-cycle BIST scheme. Reducing the number of CPs causes a corresponding degradation in the fault coverage and the scan-in pattern reduction, however, the degradation is small, e.g., when reducing the number of CPs from 201 to 70 for the b17 circuit, the fault coverage with 100k patterns decreased from 97.81% to 96.29%, scan-in patterns for 90% fault coverage increased from 130 to 185. The reduction of scan-in patterns compared to the multi-cycle test is remarkable for shortening the TAT of POST with less hardware overhead. ACM Trans. Des. Autom. Electron. Syst. Table 3: The final fault coverage reached by 100K scan-in patterns Design for Testability Approaches # of CP<1% of gates # of CP<5% of FFs Circuit SCAN 10Cycle OPI_ONLY FullOB # of CPI- # of CPI- CPI&OPI CP&FullOB CPI&OPI CP&FullOB CPs ONLY CPs ONLY s9234 87.31 84.94 89.94 90.00 55 82.69 89.68 91.80 11 83.3 87.96 88.02 s13207 90.47 84.81 92.20 92.96 79 86.16 92.75 93.89 33 85.6 90.1 91.01 s15850 87.51 87.73 88.48 90.18 104 85.09 87.41 91.52 29 86.47 87.71 90.77 s38417 141 85 95.16 97.52 97.96 98.03 98.19 98.66 98.72 98.00 98.55 98.62 s38584 91.31 90.81 91.59 92.07 97 91.16 91.70 92.28 72 90.27 90.93 91.53 b11 96.75 96.75 96.75 96.75 2 98.03 98.03 98.03 1 96.82 96.82 96.82 b12 97.28 98.64 98.68 98.68 9 99.18 99.21 99.21 6 97.6 97.6 97.64 b14 85.61 90.36 90.38 90.40 44 93.71 93.96 94.07 12 93.81 94.04 94.08 b15 69.75 92.94 92.95 92.95 8 98.35 98.36 98.36 8 98.35 98.36 98.36 b17 79.17 92.85 92.85 92.86 201 97.76 97.81 97.83 70 96.27 96.29 96.32 b20 84.69 89.52 89.66 89.69 88 93.10 93.61 93.94 24 92.68 93.17 93.22 Table 4: The number of scan-in patterns to achieve 90% fault coverage Design for Testability Approaches Circuit # of CP<1% of total gates # of CP<5% of FFs SCAN 10-Cycle OPI_ONLY FullOB # of CPs CPI-ONLY CPI&OPI CP&FullOB # of CPs CPI-ONLY CPI&OPI CP&FullOB s9234 >100K >100K >100K >100K 55 >100K >100K 9180 11 >100K >100K >100K s13207 20560 >100K 11565 7375 79 >100K 6050 4175 33 >100K 59835 8885 s15850 >100K >100K >100K 68905 104 >100K >100K 2380 29 >100K >100K 4710 s38417 5780 1710 590 460 141 250 80 55 85 310 85 60 s38584 8180 10645 3700 1960 97 1555 575 305 72 12795 960 330 b11 475 120 120 120 2 45 40 35 1 115 115 105 b12 1280 175 170 170 9 100 45 45 6 260 210 195 b14 >100K 58280 58280 53425 44 1285 870 770 12 885 675 605 b15 >100K 4180 4180 4115 8 285 230 170 8 285 230 170 b17 >100K 4305 4300 4300 201 180 130 100 70 260 185 140 b20 >100K >100K >100K >100K 88 4330 2045 935 24 7480 3740 3685 6 CONCLUSIONS The multi-cycle BIST has room for improvement to reduce the volume of scan-in patterns. Therefore, this paper investigated the stuck-at fault detection model in the time-expanded circuit. We revealed that the incompatibility between the controllability and observability of signal line as increasing the capture cycles would induce the fault masking and fault detection degradation problem. Those problems obstruct the effect of multi-cycle tests to test pattern reduction. We introduced the TPI technique to a multi-cycle LBIST scheme focused on reducing the volume of scan-in patterns for a target fault coverage to address this issue. The TPI approach replaces partial scan cells with FDS-FF referred to as OPI to enhance the observability and inserts Self-Flipping control logic into the combinational logic referred to as CPI to relax the controllability bias of signal lines of CUT at the intermediate capture cycles. ACM Trans. Des. Autom. Electron. Syst. To identify the TPs that could achieve the most scan-in pattern reduction, we proposed a metric called the CD (the degree of contribution to relax the controllability) to evaluate the effect of candidate CPI signal lines and introduced an improved probabilistic cost function for estimating the effect of CP and OP insertion under multi-cycle BIST scheme. A TPI procedure including CP insertion and OP pruning is also proposed to identify the effective TPs to achieve the most scan-in pattern reduction. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average that confirming the effectiveness of the proposed TPI for shortening the test application time of POST. In future work, we will implement the proposed TP selection algorithm to support the industrial design with Renesas Electronics Corp. to evaluate the effectiveness of the multi-cycle LBIST scheme on the commercial automotive MCUs. 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Datla Jagannadha et al.. 2019. Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. In IEEE 37th VLSI Test Symposium (VTS), pp. 1-8, https://doi: 10.1109/VTS.2019.8758636. [38] G. Mrugalski, J. Rajski, J. Tyszer and B. Włodarczak. 2022. X-Masking for In-System Deterministic Test. in IEEE European Test Symposium (ETS), pp. 1-6. https://doi: 10.1109/ETS54262.2022.9810407. ACM Trans. Des. Autom. Electron. Syst. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Design Automation of Electronic Systems (TODAES) Association for Computing Machinery

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Abstract

SENLING WANG* Graduate School of Science and Engineering, Ehime University, wang@cs.ehime-u.ac.jp XIHONG ZHOU Graduate School of Science and Engineering, Ehime University, g863003a@mails.cc.ehime-u.ac.jp YOSHINOBU HIGAMI Graduate School of Science and Engineering, Ehime University, higami@cs.ehime-u.ac.jp HIROSHI TAKAHASHI Graduate School of Science and Engineering, Ehime University, takahashi@cs.ehime-u.ac.jp HIROYUKI IWATA Renesas Electronics Corporation, hiroyuki.iwata.xg@renesas.com YOICHI MAEDA Renesas Electronics Corporation, yoichi.maeda.xd@renesas.com JUN MATSUSHIMA Renesas Electronics Corporation, jun.matsushima.vf@renesas.com Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST). Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method. CCS CONCEPTS • Integrated Circuits • Hardware Test • Design for testability Additional Keywords and Phrases: LBIST, POST, Multi-cycle Test, ISO26262, Functional Safety With the rapid evolution of technologies in developing automotive systems toward fully autonomous vehicles, various complex integrated circuits (ICs) are embedded in a car. The functional safety of the automotive system becomes a fundamental requirement as indexed by the ISO26262 standard [1]. Power-on Self-Test (POST) is the most common test solution to ensure the safety of a system. It tests the safety-critical components during the system’s startup before running any functional operations. It is thus helpful to detect any potential faults inside the components early to avoid a system failure. For testing automotive ICs, The POST needs to meet several constraints as follows. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the owner/author(s). © 2022 Copyright held by the owner/author(s). 1084-4309/2022/1-ART1 $15.00 http://dx.doi.org/10.1145/3563552 ACM Trans. Des. Autom. Electron. Syst.  Indispensable test quality: The ISO26262 standard imposes at least 90% latent fault metric to meet the most stringent automotive safety integrity level (ASIL D) for avoiding a random hardware failure (e.g., stuck-at faults) during the lifetime of ICs [1];  Limited test application time (TAT): test must be complete during the power-on reset at the engine startup (e.g., 10~50ms);  Low power: the consideration of power consumption during the test is helpful to avoid false tests under the delay fault model [2];  Low silicon overhead: suppress the increase of the Design for Test (DFT) hardware due to the ever-increasing complexity of ICs. In the past, many sophisticated solutions have been introduced to reduce the test volume of the standard LBIST, such as scan structure optimization [3, 4], the weighted random pattern [7, 8], random vector perturbing [9], Bit-flipping [10] and reseeding [11, 12, 13]. Test point insertion (TPI) technology improves the testability of CUT by inserting test logic into the CUT to deal with the detection of random pattern resistant (RPR) faults [14, 15, 16]. Other solutions focus on improving the test scheme of LBIST to enable the test-per-clock testing [17, 18], such as the shadow flip-flops insertion [19], and the Tri-Modal Scan test scheme [20] with reconfigurable scan cell design. Recently the deterministic test compression technology is also applied to the automotive ICs to run a POST or an in-system test [21, 37]. The deterministic compression test requires a modified BIST structure to allow applying the external test patterns generated by ATPG or continuous reseeding for high fault coverage. In this work, we focused on improving the test quality of an on-chip TPG-based LBIST by introducing a multi-cycle test described later to make the standard LBIST comply with the ISO26262 standard. Multi-cycle test applying more than one clock to run many times function operation after the scan -shift operation is a smart way to complement the quality of the test patterns (scan-in patterns) for test compaction [22, 23, 24], low-power testing [25, 26, 27], and logic diagnosis [28]. In a multi-cycle test, the response of CUT at each capture cycle is applied to the CUT in parallel as a capture pattern at the subsequent capture cycle. This feature is helpful to reduce the volume of scan-in patterns for attaining a target test coverage when the capture patterns can detect any additional faults that are missed by the root scan-in pattern. The multi-cycle test has the behavior to take the CUT closer to its functional operation conditions that can generate functional vectors with lower power consumption, which are very helpful to at-speed testing for delay fault detection [26, 27]. It is also easy to implement the multi-cycle test w/o the extra overhead in terms of software (e.g., modified ATPG for deterministic pattern generation) and hardware (e.g., reseeding logic & memory). Therefore, the multi-cycle test is expected to be a promising test scheme to a trade-off among the test coverage, TAT, silicon area, and low power for POST. A multi-cycle test may not always be effective for test reduction when the functional sequences generated by the CUT are not helpful to fault detection. Appropriate DFTs that can complement the value of the functional sequences are necessary to enhance the ability of the multi-cycle test to test reduction. Many DFT approaches to improve delay fault detection were presented in the past. In [29], the authors proposed a new scan cell named Transition-Launch Flip-Flop to complement the test vectors by modifying the value of partial FFs after the launch cycle in a two-cycle broadside test. In [30] and [31], the author expanded the approach of [29] to multi-cycle tests and proposed the DFT approaches to enhance the ability of the capture states to delay fault detection by holding [30] or reversing [31] the value of all FFs at the appropriate capture ACM Trans. Des. Autom. Electron. Syst. cycles. These DFT approaches considered the condition/requirement of the hard-to-detect delay faults in the multi-cycle test. In our previous works [32, 35], we have discussed the fault masking problem and the fault detection degradation problem (FDD) that would obstruct the effect of multi-cycle tests to detect stuck-at faults. It is necessary to solve the problems to reduce the test application time of POST under the indispensable test quality specified in the ISO26262 standard. The main difference between the existing DFT approaches and our works is to solve the Fault Masking and FDD problems for the stuck-at fault detection under the multi- cycle LBIST. The fault-masking problem denotes that the fault effects excited at the intermediate capture cycles might be masked before the effects are propagated to the final capture cycle for observation. To address this issue, we proposed a novel scan cell named the fault-detection-strengthened FF (FDS-FF) that directly observes and keeps the value of a faulty effect as it arrives at the FF during the capture operations [32, 33, 34]. The FDD denotes that the capability of capture patterns to detect additional stuck-at faults degrades with the increase of the number of capture cycles [35]. In [36], we have proposed a control point insertion (CPI) method to overcome the FDD by inserting control logic into scan FFs that modifies the value captured into the FFs during intermediate cycles, named the FF-CPI. While the basic idea is similar to the DFT proposed in [30, 31], our approach targeted controlling partial FFs but not the whole scan chain. We also proposed an approximate evaluation approach to identify CPs by analyzing the circuit structure without fault simulation. In general, the fault-simulation-based evaluation in [30, 31] needs more processing time than our method. Moreover, in this paper, we expand the FF-CPI approach of [36] to control the internal state of the combinational logic for stuck-at fault detection, which is different from the exiting DFT approaches will be described in Section 4. This paper consolidates the FDS-FF insertion approach denoted by OP (observation point) insertion and the FF-CPI approach into a complete DFT technique referred to as the test point insertion (TPI). Unlike the conventional TPIs which detect the random pattern resistant faults, our TPI focus on addressing the Fault Masking problem and FDD problem under a multi-cycle LBIST scheme to reduce the volume of scan-in patterns to meet the indispensable test quality specified by ISO26262. The main contributions of this paper are as follows. 1. We clarify the mechanism of Fault Masking and FDD by analyzing the stuck-at fault detection model in the multi- cycle BIST scheme. 2. We expand the FF-CPI approach to control the internal state of combinational logic by a newly proposed control logic circuit named Self-flipping CP to improve the testability for stuck-at fault detection under multi-cycle tests. 3. We propose a new metric to evaluate the effect of candidate signal lines for CP insertion under the multi-cycle BIST scheme. 4. We introduce an improved probabilistic cost function to estimate the effect of CP and OP insertion. 5. We introduce a consistent procedure to identify a user-specified number of CPs and OPs to achieve the most scan- in pattern reduction for attaining a target test coverage in the multi-cycle BIST scheme. ACM Trans. Des. Autom. Electron. Syst. 6. We evaluate the effectiveness of the proposed TPI for shortening the test application time based on the experimental results of ISCAS’89 and ITC’99 benchmark circuits under the single stuck-at fault model. The remainder of this paper is organized as follows. Section 2 introduces the basic concept of test -per- scan BIST, the multi-cycle test, and its issues. Section 3 describes the fault detection model under multi- cycle BIST. Section 4 presents the TPI approach for multi-cycle BIST. Section 5 shows the experimental results on benchmark circuits. Section 6 concludes the paper. 1 MULTI-CYCLE TEST SCHEME In this section, we first review the characteristic of scan BIST and multi-cycle BIST and discuss the problems of multi-cycle tests. 1.1 Scan BIST In a traditional test-per-scan BIST, pseudo-random vectors generated by the on-chip TPG are serially loaded into the scan chains driven by scan-shift clocks, known as scan operation. When all the scan registers are filled up, a complete scan-in pattern is latched to the inputs of the circuit. The circuit is then switched to the functional operation that generates the corresponding functional response at the outputs of the circuit. The FFs will be updated with the functional responses of the circuit when the trigger edge of the functional clock arrives, known as the capture operation. The captured functional response will be unloaded for fault detection as loading the next scan-in pattern. It is easy to observe that test is conducted only once by applying a complete scan-in pattern. Almost all test application time is consumed in the serial scan shift operation for test data delivery. 1.2 Multi-cycle BIST The multi-cycle test applies more than one functional clock to run many capture operations for every single scan-in pattern. In Figure 1, we show the operations during the multi-cycle test in the time-frame expansion of CUT. Let’s define a multi-cycle test by <s , v , c , o >, where s denotes a scan-in pattern; v denotes a i i ij i i i primary input vector; c denotes the responses of CUT captured into the scan chains represented by the ij capture patterns at the jth functional clock; o denotes a scan-out pattern which is the response of the combinational circuit when c is applied at the last capture. After a scan-in pattern s is loaded into the scan ij i chain in serial, the corresponding response c is generated at the outputs of combinational logic (FFs drawn in i1 dashed line) and captured into the FFs in parallel by the functional clock T1. Then, c is used as test stimuli i1 and latched to the circuit to generate a new response c , and c is applied and generate the corresponding i2 i2 response c in parallel until the final capture clock is applied. The response captured at the final capture o is i3 i unloaded for observation. It should be noted that the state of primary inputs v will be kept constant and the primary outputs in the intermediate capture cycle are considered unobservable during the capture operation. From Figure 1, it can be observed that conducting a multi-cycle test for each scan-in pattern <s , v > could i i provide more chances to detect additional faults through the functional capture patterns c . Therefore, it has ij promising potential to reduce the number of scan-in patterns for attaining a target test coverage that contributes to shortening the test application time due to fewer scan-shift operations. In addition, since the time of capture operation is negligible compared to the serial scan-shift operation, the reduction of the total test application time for POST is expectable. ACM Trans. Des. Autom. Electron. Syst. Primary outputs Primary inputs scan-in Combinational Combinational Combinational Combinational logic @T4 logic @T1 logic @T2 logic @T3 FF FF FF FF FF FF FF FF FF FF s o FF FF FF FF FF FF FF FF FF FF scan out c c c s i2 i3 i i1 i4 Latch clocks for s loading clocks for s loading and o unloading i T1 T2 T3 T4 i+1 i Scan shift clocks Multiple Functional Clocks M=4 Scan Enable Scan shift Mode Scan shift mode Capture Mode Figure 1. Test operations in multi-cycle BIST 1.3 The Problems of Multi-cycle BIST In our earlier works, we have raised two issues that would obstruct the effect of multi-cycle test to reduce the scan-in patterns for shortening the TAT of POST, called the Fault Masking [32, 33, 34] and Fault Detection Degradation of Capture Pattern [35, 36], respectively. The following gives a brief overview of these problems for this study. 1.3.1 Fault Masking Fault Masking denotes that the fault effects excited at the intermediate capture cycles by capture patterns might disappear before these effects are propagated to the final capture cycle for observation. Suppose that a fault f is excited at the first capture cycle by the scan-in pattern. To detect f, its faulty value has to be propagated through all M-1 capture cycles until the final capture cycle is applied. When the CUT has a deep combinational logic or the capture operation runs in a large cycle number, the time-expanded propagation path of the faulty value would become too long to be activated for detection, and the faulty value might be masked at certain logic due to the un-controllable logic state during the capture operation. Severe fault-masking would decrease the test quality of the scan-in patterns and capture patterns, and finally, obstruct the effect of the multi-cycle test for reducing the scan-in patterns. 1.3.2 Fault detection degradation problem (FDD) FDD means the capability of capture patterns to detect more additional stuck-at faults degrades as increasing the number of capture cycles. This is based on the observation that multi-cycle tests can take the CUT closer to its functional operation conditions with small internal transitions when increasing the capture cycles [26]. The functional operation would consequently cause the states of the large number of FFs to become constant when a number of capture cycles are applied. Since the value of FFs is reused as test stimuli at the ACM Trans. Des. Autom. Electron. Syst. subsequent capture cycles, the large number of FFs with constant values would cause the loss of randomness property of the capture patterns that obstructs the detection of additional faults. 2 FAULT DETECTION MODEL IN MULTI-CYCLE BIST In this section, we give a detailed analysis of the stuck-at fault detection model in a multi-cycle BIST scheme to elucidate the mechanism of Fault Masking and FDD as follows. For a stuck-at fault F , its faulty effect will always exist at each capture cycle during the capture operation, and we express it by f in the time-expanded circuit as shown in Figure 2. The faulty effect of F at each ij i capture cycle might be excited by the inputs of CUT. We use Pe to denote the probability to excite fault F ij i at the jth capture cycle. To detect F , the excited faulty value of F at the jth capture cycle (f ) must be i i ij propagated to the scan FFs for observing after the final capture, and we denote the propagation probability as Pp . ij In LBIST, Pe and Pp of a stuck-at fault F can be estimated by computing the controllability ij ij i/s ( ) and the observability ( ) of signal line i through the probabilistic random pattern testability measure such as COP (Controllability Observability Procedure). Hence, the detection probability of F at i/s the jth capture cycle denoted by Pd can be expressed by Pd = × . For a multi-cycle test with M ij/s ij/s capture cycles, the fault F would have M times opportunity to be excited by the capture patterns c ~c , i/s i1 iM and F will be detected out of once the fault is excited and propagated to the outputs. Hence, the detection i/s probability of F denoted by Pd in a multi-cycle test is the complementary probability of the case that F i/s i/s i/s cannot be excited and propagated for detection at all capture cycles, which can be expressed by: ∏ (1) Primary Primary outputs inputs scan-in Combinational Combinational Combinational Combinational logic @T4 logic @T1 logic @T2 logic @T3 FF FF FF FF FF f f f i1 i2 i3 f FF FF FF FF FF i4 × × × i i × Fi FF FF FF FF FF FF FF FF FF FF Pe i1 scan c c c c i2 s i1 i3 i4 out Pd = Pe *Pp Pd = Pe *Pp Pd = Pe *Pp Pd = Pe *Pp i1 i1 i1 i2 i2 i2 i3 i3 i3 i4 i4 i4 : Fault excitation : Faulty value propagation Figure 2. Single stuck-at fault detection in time-expanded circuit To calculate the controllability and the observability of signal lines at each capture cycle, we transform the CUT to M cycles time-frame expansion combinational circuit. We initialize the 0/1 controllability ( and ) of PI (primary input) and PPI (pseudo-primary input: FF) at the first capture cycle to 0.5/0.5, then, calculate the value of and for each gate at each time-frame. The observability of signal line at each ACM Trans. Des. Autom. Electron. Syst. time-frame is calculated starting from the PO (primary output) and PPO (pseudo-primary output) at the last capture cycle with initial value of 1.0, tracing back to the PI and PPI until the first capture cycle. Compared to the traditional scan test with a single capture, the multi-cycle test shows the potential to improve the probability of fault detection for every single scan-in pattern followed by multiple capture patterns. However, the fault detection in the multi-cycle test depends on the controllability and observability of signal lines in the time-expanded circuit, which is generally deteriorating as increasing the number of capture cycles. For demonstration, we conducted preliminary experiments on ISCAS89 and ITC99 benchmark circuits to evaluate the average 1-controllability and the observability of signal lines at each capture cycle. Figure 3 shows the results. In Figure 3. a, it can be observed that ITC99 circuits show higher 1-controllability, which implies the internal states of these circuits are easy to be 1, whereas ISCAS89 circuits likely trend to b e 0. Figure 3. b shows the standard deviation of 1-controllability of signal lines at each capture cycle corresponding to the results of Figure 3. a, to demonstrate the impact of increasing capture cycles on the controllability. The results show that the standard deviation of 1-controllability becomes higher as increasing the capture cycles, which implies the controllability of more signal lines is biasing toward either 0 or 1; in other words, the value of more signal lines in a large capture cycle would be most likely fixed at 0 or 1 during the tests. For a signal line with stuck-at fault, higher 0-controllability (0-bias) is helpful to excite the s-1 fault, whereas exciting the s-0 fault becomes difficult. Moreover, the biased controllability of signal lines in a time frame would also affect the path sensitization for propagating the excited faulty values to the FFs in the current time frame. We insist on it as the root cause of FDD observed in our previous works. ACM Trans. Des. Autom. Electron. Syst. s9234 s13207 s38584 b11 b12 b14 b15 b20 s9234 s13207 s38584 b11 b12 b14 b15 b20 0.38 0.75 0.36 0.7 0.34 0.65 0.32 0.6 0.3 0.55 0.5 0.28 0.45 0.26 0.4 0.24 0.35 0.22 0.3 0.2 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Capture Cycle Number Capture Cycle Number a. Average one-controllability of signal lines at each capture cycle b. Standard Deviation of one-controllability results at each capture cycle s9234 s13207 s38584 b11 b12 b14 b15 b20 s9234 s13207 s38584 b11 b12 b14 b15 b20 0.7 0.5 0.45 0.6 0.4 0.5 0.35 0.4 0.3 0.3 0.25 0.2 0.2 0.15 0.1 0.1 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Capture Cycle Number Capture Cycle Number d. Standard Deviation of Observability results at each capture cycle c. Average Observability of signal lines at each capture cycle Figure 3. Testability vs. Capture Cycles Regarding the observability shown in Figure 3.c and 3.d, it can be observed that in a 10-times expand circuit the value of more signal lines in earlier capture cycles is more difficult to be observed from the outputs (scan FFs) after the final capture. The deterioration of observability of signal lines at early capture cycles causes the faults excited at an early capture cycle difficult to be propagated to the final capture cycle for detection, which is the root cause of the fault masking. Based on the above analysis, we derive that the primary factor affecting the multi-cycle test to reduce the scan-in patterns for shortening the TAT of POST should be the incompatibility between the controllability and observability in the time-expanded circuit under multiple capture cycles. Where smaller 0/1 controllability bias of signal line at earlier capture cycles with lower observability. We insist that reconciling the incompatibility of testability under the multi-cycle test is necessary to improve the performance of multi-cycle BIST for scan-in pattern reduction. 3 TEST POINTS FOR MULTI-CYCLE BIST In this section, we introduce the observation point and control point proposed in our previous works [32, 33, 34, 35, 36] to address the Fault Masking and the FDD of the multi-cycle test, respectively. ACM Trans. Des. Autom. Electron. Syst. Observability 1-Controllability Standard Deviation of Observability Standard Deviation of 1-Controllability Port Function Shift Mode Capture Mode User Mode DATA FDS-FF DATA Data In don’t care 0/1 0/1 SEN SIN Scan-in 0/1 0/1 don’t care SEN Scan Enable 1 0 0 SIN Q CLK Clock 010 010 010 FF SEQ_TEST_EN Sequential 1 1 0 SEQ_TEST_EN Test Enable CLK Status !SIN DATA^!SIN DATA a. logic design of FDS-FF b. Operation mode of FDS-FF CLK Normal Scan Chain SFF SFF SFF SFF SFF CUT FDS-FF FDS-FF FDS-FF FDS-FF FDS-FF SEN FDS Scan Chain SEQ_TEST_EN CLK c. LBIST with an independent FDS-FFs scan chain Figure 4. The DFT architecture of FDS-FF insertion for LBIST. 3.1 Observation Point: FDS-FF To improve the observability of scan FFs at the intermediate capture cycles in the time-expanded circuit, we proposed a new scan-cell design named fault-detection-strengthened FF (FDS-FF) that can directly observe and keep the value of FFs captured at each cycle. Figure 4 shows the structure of FDS-FF and the DFT architecture for LBIST with FDS-FF insertion. The output of CUT denoted as DATA is controlled by scan enable signal (SEN) through a NOR gate, and a sequential test controls the scan-in test enable signal (SEQ_TEST_EN) through a NAND gate. The FDS-FF can work in three modes: Shift, Capture, and User mode as shown in the table, where Shift and Capture modes refer to as the Test mode, and User Mode refer to as the functional operation. The CUT will work at the user mode when SEQ_TEST_EN and SEN are set to 0. In Test Mode, SEQ_TEST_EN is set to 1, and the SEN signal controls the shift and the capture modes. If SEN=1, the test pattern is loaded into FF. If SEN=0, the corresponding test responses are captured. It should note that the test responses of CUT captured at each cycle are XORed with the SIN, which is the data stored in the neighbor FF in the scan chain. In this way, the test responses of each cycle can be compacted by the XOR gate, and the compacted test responses will be applied to the next capture cycle as a new test pattern. Since FDS-FFs observe and keep the capture response of CUT during the capture operation, in order to avoid functional timing issues, all FDS-FFs are extracted to constructed into a daisy chain and isolated from the other normal scan chains. ACM Trans. Des. Autom. Electron. Syst. LFSR Phase shifter MISR PI PO SI lost FF FF FF Excited 1 FF Fault FF FF FF FF FDS- FDS FDS FDS 0 lost FF FF FF FF lost FF FF FF FF SO Observe & Keep the faulty value before vanishing Figure 5. Replace a scan-FF with FDS-FF to address fault masking Figure 5 shows the effect of FDS-FF to address the fault masking problem. In a time-expanded circuit, some faulty values are successfully propagated to the FF at the intermediate capture cycles, however, would be masked before the final capture. Replacing a scan FF with the FDS-FF is equivalent to inserting an observation point into the time-expanded circuit to observe and keep these faulty values before they are masked. However, it is impractical to replace all scan-FFs with FDS-FFs, the fault effects that never pass through the selected FDS-FFs may disappear if they cannot be propagated to the final capture cycle. Fortunately, replacing a small count of scan cells with FDS-FFs could achieve significant fault detection improvement [33], which is beneficial for low hardware overhead. 3.2 Control Point: Self-Flipping CP Insert control points into the circuit to force the target signal line to 0 (0-control) or 1 (1-control) is a popular way to improve the testability of the circuit. However, it would be challenging to adapt the conventional CPI to the time-expanded circuit under multi-cycle BIST because 1) CP with a fixed control value during a complete capture operation is less helpful to relax the controllability biasing; 2) generating the control values for each capture cycle requires complex sequential ATPG; 3) applying the dynamic control value to CP during the capture operation requires intricately designed control logic. In [35, 36], we have proposed an FF-CPI approach to improve the controllability of the time-expanded circuit by modifying the captured values of partial scan FFs at each capture cycle. The FF-CP compares the state of FF at the current capture cycle with its state at the previous capture cycle and changes the current state to its inverse value if no state transition occurs on the FFs during the capture cycles. In this paper, we expand the FF-CPI approach to control the combinational logic and propose the control logic that can flip the value of the signal line of CP during the capture operation. We call it the Self-Flipping control in this paper described as follows. Figure 6 shows the design of the Self-Flipping control logic. In the capture mode, the present state (CP_OUT@T : the state of CP after the previous capture cycle) and the new state (CP_IN@T : the input i-1 i value of the candidate CP of the current capture cycle) of the CP are checked whether there is a transition occurs in the current capture cycle or not. If not, the Self-Flipping control logic will generate the inverse value of the input state to the CP output (CP_OUT@T ). An external control signal “CAP_CTR” is used to ACM Trans. Des. Autom. Electron. Syst. enable the self-Flipping when set to 1. Otherwise, the input value of CP passes through the CP logic to the output. It thus can keep the value of a target signal line at the adjacent time-frame always different to relax the bias of 0/1-controllability caused by successive capture cycles. Combinational Logic @Ti Combinational Logic @Ti-1 Scan-out FF FF FF FF FF FF CP_IN CP_OUT Candidate FF FF FF CP Scan-in a. inserting a self-flipping control point into the time-expanded circuit CP_OUT CP_IN CP_OUT CP_OUT CAP_CTR CP_IN @Ti-1 @Ti @Ti 1 0 0 1 1 0 1 1 1 1 0 0 FF 1 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 Capture clock CAP_CTR 0 1 1 1 b. self-flipping control logic c. The truth table of self-flipping control logic Figure 6. Self-Flipping CP insertion for multi-cycle LBIST It is worth noting that a traditional inversion CP using an XOR gate would be ineffective in reducing the 0/1-controllability bias because the 0/1-controllability of XOR-CP output depends on the input signal line, which is biasing as increasing the capture cycles. While inserting the Self-Flipping CP will cause hardware increase, it operates automatically during the capture cycles w/o any external control, which does not cause the extra cost in updating the ATPG to generate the control vectors. To implement the proposed multi-cycle LBIST scheme for POST, the unknown values (Xs) generated as switching the operation mode from test and function need to be dealt with carefully. This issue can be addressed by separating the control logic of POST from the test target of POST (CUTs) through wrapper logic. During the test operation, the wrapped control logic of POST will be kept in function mode. When the test is completed, the CUTs will be switched to the functional mode by a system reset through the control logic of POST. The detailed solutions to handle the implementation issues for in-system-testing have been introduced in [37, 38]. ACM Trans. Des. Autom. Electron. Syst. 4 TP SELECTION FOR MULTI-CYCLE BIST This section introduces the procedure to determine the locations of CPs and OPs to address the Fault Masking and the FDD problem induced by the controllability biasing and observation deterioration under a multi-cycle LBIST scheme. While the selection procedure inherits some underlying techniques proposed in our previous works, such as the structure-based evaluation metric and the probabilistic testability analysis of circuits for FDS-FFs and FF-CP insertion, in this paper, we consolidate them into a consistent process for TP selection under multi - cycle BIST through the following efforts:  We propose a new metric to evaluate the effect of candidate signal lines for CP insertion under a multi-cycle BIST scheme.  We introduce an improved probabilistic cost function for estimating the effect of candidate TPs.  We introduce an OP Pruning approach into the TP procedure to improve the efficiency of TP selection under the multi-cycle BIST scheme. It is worth noting that the proposed TP selection procedure conducts the probabilistic evaluation to identify the candidate CPs and Ops. The proposed TP selection procedure is a time-saving process because it does not use the conventional fault simulation. As a result, we obtain the list of the TPs, then we evaluate the fault coverage achieved under the circuit with TPs by conducting the multi-cycle test fault simulation at one time. 4.1 A new Evaluation Metrics for CP selection As discussed in Section 3, increasing the number of capture cycles would cause a significant 0/1 - controllability bias on signal lines at later capture cycles, which implies the value of more signal lines in a large capture cycle would most likely fix at 0 or 1 in most capture cycle. For a signal line x, if setting its value to 0(1) would cause fewer gates with fixed output value in its arrival logic region to FFs than that of setting to 1(0), 0(1)-controllability bias of x due to the multiple capture cycles would be helpful to fault excitation and propagation we call it positive bias, 1(0)-controllability bias would obstruct the fault detection called the negative bias. For the signal line shows a negative bias in controllability, it is suggested to insert a self-flipping CP to relax its controllability bias in the multi-cycle test. Following this, we propose the method to calculate the degree of the 0/1 controllability bias when inserting a CP into the signal line.  x: a signal line in the combinational circuit  p : the probability of line x’s value being logic 0 x/0  p : the probability of line x’s value being logic 1, where, p +p =1.0 x/1 x/1 x/0  fg : the number of gates in the arrival logic region from line x to POs/PPOs whose output value will be fixed, x/0 as setting the value of x to 0  fg : the number of gates in the arrival logic region from line x to POs/PPOs whose output value will be fixed x/1 by setting the value of x to 1  BD(x): the degree of controllability bias at line x that would impact the fault detection, where BD(x)>0 denotes a positive bias, BD(x)<0 denotes a negative bias. BD(x)=(p -p )×(fg -fg ) (2) x/0 x/1 x/1 x/0  CD(x): the degree of contribution to relax the controllability bias as forcing the 0/1-controllability of line x to 0.5/0.5. CD(x)>0 denotes a positive contribution, CD(x)<0 denotes a negative contribution that would be achieved by CP insertion. ACM Trans. Des. Autom. Electron. Syst. CD(x)=(p -0.5)×fg +(p -0.5)×fg =(0.5-p )×(fg -fg ) (3) x/0 x/0 x/1 x/1 x/0 x/1 x/0 We use the s27 circuit as an example for illustration, see Figure 7. For signal line i, two paths connect with the PPO (FF2) through path 1: i → G5 → G7 → G8 → w, and path 2: i → G6 → G7 → G8 → w. When the value of i is 1, the output of G5, G6, and G7 will be fixed at 1, 1, 0, respectively, thus fg =3. i/1 When i is 0, the output of G5 and G6 depends on the other input signal lines n and c, which implies a 0 value at i cannot directly cause any fixed gates on the two paths to FFs, thus fg =0. The probability of signal i/0 line i’s values p and p can be calculated using the COP measurement, which is 0.25 and 0.75. The degree i/1 i/0 of controllability bias is hereby BD(i) = 0.5×3 = 1.5, which represents that the controllability bias at signal line i is positive to fault detection. For the signal line with positive controllability bias, inserting a CP would cause more fixed gates on the fault propagation paths to FFs with a negative contribution to fault detection, e.g., CD(i)=-0.25×3=-0.75. Table 1 gives the evaluation value of some signal lines shown in Figure 7. It can be observed that signal lines q and s show the negative controllability bias in BIST, and inserting a CP to s would achieve the most contribution to fault detection. Figure 7. The combinational logic frame of s27 circuit Table 1: evaluation metrics of signal lines in s27 line # fg fg p p BD CD x/0 x/1 x/0 x/1 h 0 2 0.75 0.25 1 -0.5 i 0 3 0.75 0.25 1.5 -0.75 n 0 1 0.75 0.25 0.5 -0.25 q 3 0 0.56 0.44 -0.36 0.18 s 0 2 0.27 0.73 -0.92 0.46 As shown in Figure 3, the controllability bias on signal line changes at different capture cycles in the multi-cycle BIST. It becomes larger as increase the number of capture cycles. Thus, the degree of ACM Trans. Des. Autom. Electron. Syst. controllability bias of signal line x: BD(x) and the contribution of CP insertion to relax the impact of controllability bias on fault detection: CD(x) can be easily extended for the multi-cycle test as follows. ∑ (4) (5) where p and p denote the probability of line x’s value being logic 1/0 at the jth capture cycle. We use CD as the xj/1 xj/0 evaluation metrics for searching the candidate signal lines for CP insertion under multi-cycle BIST, which is described in the next section. 4.2 TP Selection Procedure for Multi-cycle BIST The procedure consists of two phases, Phase 1: CP insertion under a time-expanded circuit with full FF- observation, and Phase 2: OP is pruning to remove the impotent observation points (FDS-FF). In Phase 1, the CP selection will be performed at the time-expanded circuit with full observation where the FFs at intermediate capture cycles are supposed to be observable. This is because the purpose of self- flipping CP insertion is to relax the controllability bias caused by functional operation at each time frame, but not to create long propagation paths that can cross multiple time frames to the final capture cycle for observation which is an arduous task. The algorithm for CP insertion is shown in Algorithm 1. To evaluate the quality of CPs and OPs, cost function U as follows is widely used in various TPI techniques. (6) In this work, we expand the cost function considering the fault detection model under the multi-cycle BIST scheme, where the detection probability of the faults at a signal line denoted by Pd is calculated by x/s ∏ (7) C and O denote the s-controllability and observability of signal line x at the jth time-frame, respectively, computed by xj/s xj org tp COP measure as discussed in Section 3. The difference in U before (U ) and after (U ) inserting a TP can be calculated by the following equation to identify the most effective TP from a candidate TP list. (8) In Phase 2, we will remove the impotent observation points from the time-expanded circuit to reduce the hardware overhead caused by FDS-FFs insertion, named OP pruning, as shown by Algorithm 2. In OP pruning, the input is the time-expanded circuit with CP insertion achieved at Phase 1 where all scan FFs are replaced with FDS-FFs for observation during multi-cycle captures. We target on reducing the amount of FDS-FFs to a user-specified number N by restoring the FDS-FFs that do not affect the fault detection to op ACM Trans. Des. Autom. Electron. Syst. scan FFs. As shown from line 14 to line 24 of algorithm 2, we compute the cost U of each candidate FDS-FF when temporarily changing it to a scan FF which is equivalent to a wire in the intermediate time-frame circuit, and remove the one which has the least cost increase from the OP list. The OP pruning is considered effective based on the following observations. 1) The large number of signal lines usually can be observed by multiple FFs; 2) The FFs which have larger observable logic regions could observe more fault effects. 3) The number of FFs in a design is much smaller than that of signal lines, and exploring the inactive FFs would be more time-saving than inserting OPs into the CUT. ALGORITHM 1: CP insertion Inputs: net: original CUT netlist M: the number of capture cycles N : Maximum number of CPs cp Outputs: cplist[N ]: Selected CP list cp net : CUT with CP insertion cp Optional parameter: CR : the threshold of cost reduction (≥0) threshold N : number of candidate CP at each iteration of CP decision cand Process: 1: cplist ← 2: cand ← /*Candidate CP list for determining a CP*/ 3: read_circuit (net); 4: fix_gate_cal(net); /*computing fg , fg */ x/0 x/1 5: time_expansion (net, M); 6: full_observation_point_insertion( ); 7: while |cplist|< N do cp 8: cop_controllability(net ); cp 9: cop_observability(net ); cp 10: CD_calculate (net ); cp 11: cand ← ; 12: for j=1 to # of available candidate CP do 13: cand[j] ←unchecked signal line with the largest CD; 14: end for 15: if cand= then 16: return cplist, net ; stop the process cp 17: else org 18: U =cost_computation(net ,M); cp 19: for k=1 to N do cand 20: net =insert cand[k] cp to net ; cp cp 21: update_controllablity_observability(net , M); cand[k] org 22: =U -cost_computation(net , M); cp 23: Remove cand[k] from net ; cp 24: end for 25: If maximum( )>= CR then k threshold ACM Trans. Des. Autom. Electron. Syst. 26: cplist[i]←cand[k]; 27: end if 28: end if 29: insert cplist[i] to net → update net ; cp 30: end while 31: return cplist, net ; cp end process ALGORITHM 2: OP Pruning Inputs: net : CUT with CP insertion cplist M: number of capture cycles N :Target number of OPs (FDS-FFs) op Outputs: oplist[N ]: FF list for FDS-FFs insertion op net : CUT with TPs (CP and OP) tp Optional parameter: N : # of candidate OPs at each iteration for OP pruning cand Process: 1: oplist ← 2: cand ← /* Candidate target OP list for pruning */ 3: read_circuit (net ); cp 4: oplist← all FFs 5: structure_analysis(net ); cp 6: FF_ranking(oplist) /*Ranking the FFs by the approximate evaluation metrics proposed in [39]*/ 7: while |oplist|>N do op 8: for j=1 to # of available candidate OP do 9: cand[j] ←select an OP in the oplist in descending order which is unchecked; 10: end for 11: if cand= then 12: return oplist, net ; stop the process tp 13: else org 14: U =cost_computation(net ,M); tp 15: for k=1 to N do cand 16: remove cand[k] OP from net ; tp 17: update_observability(net ); tp org 18: =U -cost_computation(net , M); tp 19: restore cand[k] OP to net ; tp 20: end for 21: If =minimum then 22: remove cand[k] OP from net ; tp 23: remove cand[k] from oplist; 24: end if 25: end if 26: end while 27: return oplist, net ; tp end process ACM Trans. Des. Autom. Electron. Syst. 5 EXPERIMENTAL RESULTS Experiments are conducted on ISCAS89 and ITC99 benchmark circuits to evaluate the effect of TPI under 16 15 13 4 multi-cycle BIST. A 16-bits internal type LFSR (characteristic polynomial: X +X +X +X +1) with Phase Shifter generates pseudo-random patterns. A parallel scan structure is introduced into the CUT that consists of multiple scan chains up to 100 FFs in length (when the total number of FFs > 1600, the maximum length of the chain is up to 200). A multi-cycle BIST logic/fault simulator that can simulate at most 50 cycles capture per pattern is implemented in-house for stuck-at faults testing. For automotive ICs, the ISO26262 functional safety standard imposes at least 90% latent fault metric (permanent fault) to meet the safety goal ASIL D. Therefore, in this study, we set a target fault coverage 90% and evaluate the effect of the proposed multi-cycle TPI that would make the classical on-chip pseudo-random TPG-based LBIST comply with the ISO26262 standard. Table 2 gives the details of CUTs. Table 2: Detailed information of benchmark circuits # of N N #OPs (FDS-FFs) cp cp Circuit # gate # FF stuck-at fault (<1% of gates) (<5% of FFs) (<20% of FFs) s9234 5597 228 6927 55 11 45 s13207 7951 669 9815 79 33 133 s15850 9772 597 11725 104 29 120 s38417 22179 1636 31180 1141 85 327 s38584 19253 1452 36303 97 72 290 b11 437 31 1322 2 1 6 b12 904 121 2797 9 6 24 b14 4444 245 12811 44 12 49 b15 8338 449 23528 8 8 89 b17 22645 1415 65464 201 70 283 b20 8875 490 25338 88 24 98 5.1 Evaluation of the efficiency of the multi-cycle test We first performed fault simulations on the regular scan testing with single capture (SCAN) and multi-cycle testing with 2, 4, 6, 8, and 10 capture cycles, respectively, to evaluate the effect of multi-cycle testing for fault detection, using 100k test patterns (scan-in) generated by LFSR. Figure 8 shows the fault coverage of each circuit at different capture cycles when 100k patterns are applied. It can be seen that for most circuits, the multi-cycle test achieved an increase in fault coverage at the 2 and 4 capture cycles. As continuously increasing the capture number to 10 cycles, the increment of fault coverage is slowing down or getting degraded. For s9234, the multi-cycle test shows a significant decrease in fault coverage. It can be explained by the incompatibility of testability shown in Figure 3, where the 10-cycle test caused a little controllability bias, however, significant deterioration of the observability in the expanded circuit. ACM Trans. Des. Autom. Electron. Syst. scan 2-cycle 4-cycle 6-cycle 8-cycle 10-cycle s9234 s13207 s15850 s38417 s38584 b11 b12 b14 b15 b17 b20 Figure 8: fault coverage of benchmark circuit with 100k patterns Effect of multi-cycle test on the fault detection of benchmark circuits SCAN 2cycles 4cycles 6cycles 8cycles 10cycles # of scan-in patterns Figure 9: scan testing vs multi-cycle testing Figure 9 shows the curve of the average fault coverage of all CUTs by increasing the number of patterns. The horizontal and vertical axis shows the pattern number and the corresponding fault coverage, respectively. The average fault coverage of all CUTs confirms that the multi-cycle test has a statistical improvement in fault detection for most benchmark circuits compared with scan testing (SCAN). Applyi ng 4 ACM Trans. Des. Autom. Electron. Syst. Fault Coverage(% ) Fault Coverage (%) 98535 and 6 capture cycles achieved the most fault coverage improvement, and the increment of fault coverage becomes less as the number of capture cycles increases to 8 and 10 cycles. The above observations fit the basic feature of multi-cycle testing discussed in Section 3. Multiple capture operations would provide more detection opportunities for the fault that the scan-in pattern cannot detect. Therefore, it is possible to improve the fault detection of the scan-in pattern. However, the deterioration of testability of signal lines in the time-expanded circuit would interfere with future fault detection as increasing the capture cycles. To reinforce the effect of multi-cycle BIST on scan-in pattern reduction, CP insertion and FDS-FFs insertion are introduced, and their effects are described as follows. 5.2 Evaluation of the efficiency of the CPI and the OPI We conducted the CP selecting and OP pruning algorithm proposed in Section 5 on the benchmark circuits to identify a specified amount of CPs and FDS-FFs, where the maximum number of CPs N was set to 1% of cp the gate number of CUT, and 5% of the FFs, respectively. The expected amount of FDS-FFs is set to 20% of the total number of FFs in the CUT. The number of CPs and FDS-FFs are shown in the fifth and the sixth column of Table 2, respectively. To demonstrate the difference between OPI and CPI, we performed fault simulation under 10 cycles by individually inserting the identified CPs and OPs into the CUTs, denoted by CP-ONLY and OP-ONLY, respectively. CPI&OPI denotes inserting both the CPs and OPs into the CUTs. Figure 10 shows the curve of average fault coverage of the benchmark circuits, increasing scan-in patterns to 100K under different DFT strategies. The figure only presents the curves up to 50K patterns for demonstration. Full observation replaces all FF with FDS-FFs has been conducted on the CUTs w/(w/o) CP insertion denoted by FullOB, CP&FullOB, respectively. While it is not for practical use due to hardware overhead concerns, the results represent the upper bound of the fault coverage possibly achieved by OPI, which is used to evaluate how far the OP pruning has reached in identifying the OPs for FDS-FFs insertion. ≒24.4X reduction 585 by CPI&OPI 14260 scan-in patterns by 10-Cycle Test to gain 90% fault coverage 2195 by CPI_ONLY 5175 by OPI_ONLY + + + SCAN 10-Cycle OPI_ONLY FullOB CPI-ONLY CPI&OPI CP&FullOB Number of Scan-in Patterns Figure 10: Fault coverage vs. Pattern number (scan testing, multi-cycle testing, OPI and CPI under multi-cycle testing). ACM Trans. Des. Autom. Electron. Syst. Fault Coverage (%) 49585 Compared to the regular scan test (SCAN), the multi-cycle test w/o TPI denoted by “10-Cycle” in the figure achieved a significant fault coverage improvement where a target fault coverage (90%) is attained by applying 14,260 scan-in patterns under a 10-cycle test, which cannot be achieved by scan testing even with more than 100K scan-in patterns. Replacing 20% of FFs with FDS-FFs (OPI-ONLY) further improved the fault coverage and reduced the necessary scan-in patterns to 5,175 for the target 90% fault coverage as well as the effect achieved by full observation (replacing all scan FFs with FDS-FFs). The results demonstrate the effect of FDS-FFs insertion that directly observes the values of FFs at each capture cycle to relax the fault masking problem in the time-expanded circuit. Note the fault coverage curve of CPI-ONLY in Figure 10, where we inserted 1% of the gate number of CPs into the CUTs, and it shows almost the same fault coverage improvement (≈93%) and much more scan- in pattern reduction (2,195 for 90% fault coverage) than that of OPI-ONLY. The results indicate 1) inserting Self-Flipping CP into the CUT that relaxes the controllability bias in a time-expanded circuit is helpful in improving the fault detection of capture patterns 2) the effect of CPI is limited due to the fault masking problem in the time-expanded circuit. When inserting both the identified CPs and OPs into the CUTs denoted by CPI&OPI, we achieved a sharp increase in fault coverage compared to inserting CPs and OPs individually. The final fault coverage of 100K scan-in patterns increases to 95.01%. The number of scan-in patterns for achieving 90% fault coverage is drastically reduced to 585 (24.4X reduction compared to the multi-cycle test). Note the fault coverage curve of 10-cycle (multi-cycle test) and the CP&FullOB, which represents the upper bound of the fault coverage possibly achieved by CPI&OPI, inserting both the CPs and OPs (CPI&OPI) identified by our proposed method achieved remarkable fault coverage increase and pattern reduction that is very close to the upper bound. Table 3 and Table 4 show the detailed results of the final fault coverage achieved by applying 100K patterns and the number of scan-in patterns for attaining 90% stuck-at fault coverage, respectively. The experimental results when inserting fewer CPs (<5% of FFs) into the benchmark circuits are also presented in the tables. The results show that the 10-cycle test would cause the fault coverage loss in most ISCAS89 circuits (s9234, s13207, s38584); however, it achieves a significant increase in ITC99 benchmark circuits. Where ISCAS89 circuits show a much more testability bias, increasing the capture cycles are vulnerable to fault masking and FDD problem. While inserting OP or CP individually both improved the fault coverage and reduce the patterns for attaining 90% fault coverage for all circuits, it suggests that combining the CPs and OPs can achieve the most pattern reduction under the multi-cycle BIST scheme. Reducing the number of CPs causes a corresponding degradation in the fault coverage and the scan-in pattern reduction, however, the degradation is small, e.g., when reducing the number of CPs from 201 to 70 for the b17 circuit, the fault coverage with 100k patterns decreased from 97.81% to 96.29%, scan-in patterns for 90% fault coverage increased from 130 to 185. The reduction of scan-in patterns compared to the multi-cycle test is remarkable for shortening the TAT of POST with less hardware overhead. ACM Trans. Des. Autom. Electron. Syst. Table 3: The final fault coverage reached by 100K scan-in patterns Design for Testability Approaches # of CP<1% of gates # of CP<5% of FFs Circuit SCAN 10Cycle OPI_ONLY FullOB # of CPI- # of CPI- CPI&OPI CP&FullOB CPI&OPI CP&FullOB CPs ONLY CPs ONLY s9234 87.31 84.94 89.94 90.00 55 82.69 89.68 91.80 11 83.3 87.96 88.02 s13207 90.47 84.81 92.20 92.96 79 86.16 92.75 93.89 33 85.6 90.1 91.01 s15850 87.51 87.73 88.48 90.18 104 85.09 87.41 91.52 29 86.47 87.71 90.77 s38417 141 85 95.16 97.52 97.96 98.03 98.19 98.66 98.72 98.00 98.55 98.62 s38584 91.31 90.81 91.59 92.07 97 91.16 91.70 92.28 72 90.27 90.93 91.53 b11 96.75 96.75 96.75 96.75 2 98.03 98.03 98.03 1 96.82 96.82 96.82 b12 97.28 98.64 98.68 98.68 9 99.18 99.21 99.21 6 97.6 97.6 97.64 b14 85.61 90.36 90.38 90.40 44 93.71 93.96 94.07 12 93.81 94.04 94.08 b15 69.75 92.94 92.95 92.95 8 98.35 98.36 98.36 8 98.35 98.36 98.36 b17 79.17 92.85 92.85 92.86 201 97.76 97.81 97.83 70 96.27 96.29 96.32 b20 84.69 89.52 89.66 89.69 88 93.10 93.61 93.94 24 92.68 93.17 93.22 Table 4: The number of scan-in patterns to achieve 90% fault coverage Design for Testability Approaches Circuit # of CP<1% of total gates # of CP<5% of FFs SCAN 10-Cycle OPI_ONLY FullOB # of CPs CPI-ONLY CPI&OPI CP&FullOB # of CPs CPI-ONLY CPI&OPI CP&FullOB s9234 >100K >100K >100K >100K 55 >100K >100K 9180 11 >100K >100K >100K s13207 20560 >100K 11565 7375 79 >100K 6050 4175 33 >100K 59835 8885 s15850 >100K >100K >100K 68905 104 >100K >100K 2380 29 >100K >100K 4710 s38417 5780 1710 590 460 141 250 80 55 85 310 85 60 s38584 8180 10645 3700 1960 97 1555 575 305 72 12795 960 330 b11 475 120 120 120 2 45 40 35 1 115 115 105 b12 1280 175 170 170 9 100 45 45 6 260 210 195 b14 >100K 58280 58280 53425 44 1285 870 770 12 885 675 605 b15 >100K 4180 4180 4115 8 285 230 170 8 285 230 170 b17 >100K 4305 4300 4300 201 180 130 100 70 260 185 140 b20 >100K >100K >100K >100K 88 4330 2045 935 24 7480 3740 3685 6 CONCLUSIONS The multi-cycle BIST has room for improvement to reduce the volume of scan-in patterns. Therefore, this paper investigated the stuck-at fault detection model in the time-expanded circuit. We revealed that the incompatibility between the controllability and observability of signal line as increasing the capture cycles would induce the fault masking and fault detection degradation problem. Those problems obstruct the effect of multi-cycle tests to test pattern reduction. We introduced the TPI technique to a multi-cycle LBIST scheme focused on reducing the volume of scan-in patterns for a target fault coverage to address this issue. The TPI approach replaces partial scan cells with FDS-FF referred to as OPI to enhance the observability and inserts Self-Flipping control logic into the combinational logic referred to as CPI to relax the controllability bias of signal lines of CUT at the intermediate capture cycles. ACM Trans. Des. Autom. Electron. Syst. To identify the TPs that could achieve the most scan-in pattern reduction, we proposed a metric called the CD (the degree of contribution to relax the controllability) to evaluate the effect of candidate CPI signal lines and introduced an improved probabilistic cost function for estimating the effect of CP and OP insertion under multi-cycle BIST scheme. A TPI procedure including CP insertion and OP pruning is also proposed to identify the effective TPs to achieve the most scan-in pattern reduction. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average that confirming the effectiveness of the proposed TPI for shortening the test application time of POST. In future work, we will implement the proposed TP selection algorithm to support the industrial design with Renesas Electronics Corp. to evaluate the effectiveness of the multi-cycle LBIST scheme on the commercial automotive MCUs. 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Journal

ACM Transactions on Design Automation of Electronic Systems (TODAES)Association for Computing Machinery

Published: May 10, 2023

Keywords: LBIST

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