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A New Model of Dynamic Logic Circuit with NMOS based Keeper

A New Model of Dynamic Logic Circuit with NMOS based Keeper AbstractDynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Acta Universitatis Sapientiae Electrical and Mechanical Engineering de Gruyter

A New Model of Dynamic Logic Circuit with NMOS based Keeper

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Publisher
de Gruyter
Copyright
© 2020 Riazul Islam et al., published by Sciendo
eISSN
2066-8910
DOI
10.2478/auseme-2020-0001
Publisher site
See Article on Publisher Site

Abstract

AbstractDynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.

Journal

Acta Universitatis Sapientiae Electrical and Mechanical Engineering – de Gruyter

Published: Dec 1, 2020

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