A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node
A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm...
Yin, Jiayu;Liao, Wenli;Chen, Chengying
2023-02-14 00:00:00
Hindawi Active and Passive Electronic Components Volume 2023, Article ID 2364341, 11 pages https://doi.org/10.1155/2023/2364341 Research Article A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node Jiayu Yin, Wenli Liao, and Chengying Chen School of Opto-Electronic and Communication Engineering, Xiamen University of Technology, Xiamen 361024, China Correspondence should be addressed to Chengying Chen; chenchengying363@163.com Received 5 November 2022; Revised 23 January 2023; Accepted 3 February 2023; Published 14 February 2023 Academic Editor: Gerard Ghibaudo Copyright © 2023 Jiayu Yin et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With diferential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. Te nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/ read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. Te data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm . Garbin et al. proposed the 6T2R nvSRAM structure [5], 1. Introduction which parallels a pair of RRAMs on the storage nodes and SRAM is a well-known high-speed and low-power cache. uses the high- and low-resistance states of RRAM to realize However, when the system is powered of, the data of the data storage. But the stability of SRAM will also decline, and the existence of DC short-circuit current will increase power storage node cannot be saved, which limits the use of SRAM in applications. For ATM, railway controller, and other consumption. An 8T2R nvSRAM cell is presented in [6], equipment, it is necessary to store real-time data in case of which controls the conduction branch by adding two MOS power failure. After the power supply of the system rises, the transistors in series with RRAM, so as to avoid DC short- data can be restored to the original state. EEPROM, EPROM, circuit current of 6T2R structure. Te structure adopts Flash, and other nonvolatile memories can store data in real diferential mode and has good data restoration efciency. time, but they all have some performance problems. In Turkyilmaz et al. proposed a RRAM-based FPGA solution recent years, in order to solve the volatile problem of SRAM, [7], integrating the nonvolatile RRAM into the confguration academia and industry have begun to study nvSRAM. unit and register, so as to restore FPGA data immediately. Te scheme adopts 22 nm LETI-FDSOI process and Compared with traditional SRAM, nvSRAM has the same performance and nonvolatile function, which provides nvSRAM with 8T2R structure. Te increased control signal will increase the chip area in this structure. Wei et al. guarantee for high-end instruments and equipment to store data in real time. proposed a 7T1R structure [8]. Tis scheme adopts single As a new nonvolatile memory, RRAM has the advan- mode and directly adds a 1T1R memory cell to the storage tages of high density, low-power consumption, and com- node of SRAM. Compared with the structure of 8T2R, this patibility with the CMOS technology. Terefore, based on structure has higher integration and high-fault margin in the nonvolatile and high stability of RRAM, various data restoration, but MOS and NVM devices are greatly nvSRAM memory cell structures combined with RRAM are afected by the process. In the 6T2R nvSRAM [9], the load proposed. Table 1 summarizes the advantages and disad- PMOS of SRAM is replaced by RRAM, and the access vantages of the four mainstream NVMs. transistor is replaced by the transmission gate. Te cell has 2 Active and Passive Electronic Components Table 1: Four mainstream NVMs. BL BLB MRAM RRAM NVM FERAM [1] PCM [3] VD [2] [4] Read speed 20–80 ns 3–20 ns 20–50 ns 10–50 ns Write/erase 50/ 50/50 ns 3–20 ns 10–50 ns MP1 MP2 speed 120 ns Resistance ratio >8 2 >10 >10 WL WL Power Low High Low Low consumption Supply voltage 2-3 V 3 V 1.5–3 V 1.5–3 V Q QB MN4 MN3 Process Incompatible Low High High compatibility Integration Low High High High MN1 MN2 fast read-write speed and low-static power consumption, but VS the introduction of transmission gate may cause destructive Figure 1: 6T SRAM. operation when reading data. In view of the above shortcomings, an improved 8T2R nvSRAM memory cell is proposed and implemented by a BL RBL RBLB BLB UMC 28 nm process in this study. By optimizing the RRAM connection mode and using the diferential data storage/ VD RRAM1 RRAM2 restoration mode, the structure not only reasonably opti- mizes the area but also improves the data storage ability. It RWL RWL MN5 MP1 MP2 MN6 also obtains better noise margin and fast data storage/res- WL WL toration time. MN3 QB MN4 2. Memory Cell Design MN1 MN2 Te memory cell of nvSRAM is mainly composed of SRAM and nonvolatile cells. SRAM adopts the traditional 6T SRAM structure, as shown in Figure 1. Transistors VS MP1 and MN1 form a left inverter, and MP2 and MN2 Figure 2: 8T2R nvSRAM. form a right inverter. Te two inverters are crosscoupled to store data. MN3 and MN4 are access transistors. Storage nodes Q and QB are, respectively, connected to BL and BLB through access transistors. WL is the gate control NMOS transistor is connected to the storage node and the other end is connected to the lower electrode of the signal of access transistors. Only when WL is turned on can the memory be read and written. Te previous RRAM. Te transistor gate is controlled by the new signal nvSRAM memory cell mainly includes 6T2R, 7T1R, and RWL, and the upper electrode of the RRAM is controlled 8T2R. Te structure of 6T2R adds a pair of RRAM to the by the new signal RBL and RBLB, respectively, and CMOS storage nodes. In case of system failure, the data are di- 28 nm 1p9m process is adopted which makes the core rectly stored in RRAM to avoid data loss. Due to the DC device have great driving ability and good stability. Since path between storage node and RRAM, the leakage of bipolar RRAM is used, when RRAM performs set and memory and the increase of power consumption are reset operations, diferent voltages are applied to its upper caused. 7T1R structure adds a 1T1R nonvolatile memory and lower electrodes to control the resistance change. Te to its storage node, which isolates the RRAM from the upper electrodes of RRAM are introduced into inde- storage node through MOS transistor and solves the pendent control signals, respectively, and the resistance value of RRAM is controlled through driving circuit and problems of leakage and power consumption in 6T2R cell. But the single-ended data writing will result in high-fault power control circuit. Only when the RWL signal is tolerance rate, and its asymmetry will afect the density of turned on can the data of SRAM and RRAM be trans- memory array. 8T2R cell adopts diferential structure, mitted, so that the static power consumption is zero when which has high stability when storing data. However, the NVM is not working. when RRAM performs set and reset operations, higher During normal operation, nvSRAM only performs read operating voltage is required, which brings some chal- and write. When the power supply voltage drops or turns of, lenges to the design of peripheral circuits. the system switches to data storage mode and the data are Te improved 8T2R nvSRAM memory cell proposed stored to RRAM. When the voltage of SRAM recovers, the data start to restore, and the data in RRAM will be restored in this study is shown in Figure 2. Diferent from the previous 8T2R cells, in the 1T1R structure, one end of the to the storage node of SRAM. Active and Passive Electronic Components 3 RBLB (RVD/0) Te data storage operation is shown in Figure 3. When BL RBL (RVD/0) BLB Q � 0, QB � 1, RRAM1 and RRAM2 are in the state of high- VD (RVD) H L RRAM1 H L RRAM2 and low-resistance, respectively. When the system power Set Reset supply of nvSRAM fails, nvSRAM switches to data storage RWL (VWL) RWL (VWL) MN5 MP1 MP2 MN6 mode. At this time, VD switches to RVD. Te voltage of WL WL node QB rises to RVD with the change of VD, and Q is always low. Meanwhile, RBL and RBLB are high. When RWL is turned on, the upper and lower electrodes of QQB MN4 MN3 RRAM1 have a large voltage diference. A set operation is carried out, and the resistance of RRAM2 remains un- MN1 MN2 changed. When both RBL and RBLB are low and RWL is turned on, RRAM2 performs reset operation. Ten, RRAM1 VS resistance remains unchanged. By controlling RBL, RBLB, Figure 3: Data storage operation. and the system power supply of nvSRAM, the bipolar RRAM resistance value can be changed, so as to achieve the purpose of data storage. Te data restoration operation is shown in Figure 4. Te BL RBL (0) RBLB (0) BLB two RRAMs are in the state of low- and high-resistance, 0 VD L H RRAM1 RRAM2 respectively. At this moment, the power supply voltage is low and no data is stored in the storage node. When the power RWL (VD) RWL (VD) MN5 MP1 MP2 MN6 supply gradually rises from 0 to VD and RWL is turned on, WL WL the voltage of RBL and RBLB becomes low through the control of read drive circuit. When decoded by the clock 0 MN3 MN4 QB control circuit and the address decoding control circuit, the RWL is high, making MN5 and MN6 turn on. Te con- MN1 MN2 duction of MN6 makes the voltage of RRAM2 gradually higher, while the conduction of MN5 makes the voltage of VS RRAM1 gradually lower. When the power supply is restored, the voltage of the two storage nodes is restored to low and Figure 4: Data restoration operation. high, respectively. BL (VD) BLB (VD) 3. Memory Cell Size Analysis VD In reading process, if the memory cell is not designed properly, it will make data read incorrectly. Tis phenom- enon is called destructive reading problem. In order to avoid MP2 MP1 this problem, the transistor size of memory cell must meet WL (VD) WL (VD) certain requirements. Te read operation of nvSRAM is QB=0 shown in Figure 5. When Q � 1 and QB � 0, the voltages of Q=1 the two-bit lines and WL are high, MN3 and MN4 are on at n2 MN4 MN3 this time, and BLB, MN4, and MN2 form a path from power supply to ground. If the size of MN4 is larger than MN2, it is ΔV equivalent to two transistors dividing the voltage of BLB, and MN2 MN1 the large size of MN4 makes the storage node QB have a large voltage. When the voltage of Vn2 is greater than the threshold of MN1, the voltage of the storage node will fip, VS resulting in the loss of original data. To avoid the problem of destructive readout, when Figure 5: Read operation. designing memory cell size, it must ensure that the voltage of Vn2 is less than the fip threshold Vs of the left inverter. In the best case, the voltage of Vn2 is less than the threshold of saturation region and MN2 works in the linear region. Assuming that the fip threshold Vs of the inverter is half of transistor MN1 to avoid turning on MN1. At this time, when the voltage of bit line BLB is approximately equal to power the power supply voltage, that is, Vn2 � Vs � VDD/2, and VBLB � VD. Ten, substitute it into the current equation of supply voltage VDD and node QB does not make an error, the transistor. Since the currents of MN3 and MN2 are the the voltage of Vn2 is less than the fip threshold Vs of the left same, equation (1) is obtained. Meanwhile, the cell ratio inverter. By analyzing the state of each transistor at the (CR) of the memory cell is defned, as shown in equation (2). critical point, it can be seen that MN3 works in the 4 Active and Passive Electronic Components the path between the power supply and BLB. Only when the k V V V n,MN3 DD DD DD − V � k