Get 20M+ Full-Text Papers For Less Than $1.50/day. Start a 14-Day Trial for You or Your Team.

Learn More →

A Combined Data and Power Management InfrastructureThe CCSDS Decoder/Encoder Boards

A Combined Data and Power Management Infrastructure: The CCSDS Decoder/Encoder Boards [Traditionally the implementation of Telemetry Encoders and Telecommand Decoders for space has been made in hardware, at least for the last two decades. This was also the approach that was envisaged when these OBC boards had been conceptualized. But with the availability of more processing power (e.g. the LEON3FT 32-bit fault-tolerant SPARCTM V8 processor), more of the encoding and decoding tasks can be moved to software, allowing flexibility for adapting the system to on-going standardization efforts. The approach followed here in this CDPI architecture is that part of the CCSDS decoding/encoding is performed in an IP.core on FPGA hardware on the CCSDS decoder/encoder board and part of the task is done in software using libraries. This firmware and software was provided by Aeroflex Gaisler AB together with the RTEMS realtime operating system for the Aeroflex Processor-Boards cited in Chap. 2.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Combined Data and Power Management InfrastructureThe CCSDS Decoder/Encoder Boards

Part of the Springer Aerospace Technology Book Series
Editors: Eickhoff, Jens

Loading next page...
 
/lp/springer-journals/a-combined-data-and-power-management-infrastructure-the-ccsds-decoder-0BN0YqH0Cx

References (0)

References for this paper are not available at this time. We will be adding them shortly, thank you for your patience.

Publisher
Springer Berlin Heidelberg
Copyright
© Springer-Verlag Berlin Heidelberg 2013
ISBN
978-3-642-35556-1
Pages
59 –102
DOI
10.1007/978-3-642-35557-8_4
Publisher site
See Chapter on Publisher Site

Abstract

[Traditionally the implementation of Telemetry Encoders and Telecommand Decoders for space has been made in hardware, at least for the last two decades. This was also the approach that was envisaged when these OBC boards had been conceptualized. But with the availability of more processing power (e.g. the LEON3FT 32-bit fault-tolerant SPARCTM V8 processor), more of the encoding and decoding tasks can be moved to software, allowing flexibility for adapting the system to on-going standardization efforts. The approach followed here in this CDPI architecture is that part of the CCSDS decoding/encoding is performed in an IP.core on FPGA hardware on the CCSDS decoder/encoder board and part of the task is done in software using libraries. This firmware and software was provided by Aeroflex Gaisler AB together with the RTEMS realtime operating system for the Aeroflex Processor-Boards cited in Chap. 2.]

Published: Jun 14, 2013

Keywords: Direct Memory Access; Code Layer; Convolutional Encoder; Start Sequence; Transfer Frame

There are no references for this article.