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A New Generation of Cosmic Superstring SimulationsSupercomputing with Graphics Processing Units

A New Generation of Cosmic Superstring Simulations: Supercomputing with Graphics Processing Units [For well over a decade, the empirical Moore’s law (a doubling in transistor count should occur every 18-24 months, courtesy of refined manufacturing processes) has been upheld. Up until the early 2000’s the way to use these extra transistors was to create more complex processors, larger caches and much faster clock frequencies. However, this eventually proved unfeasible: simply increasing clock frequencies in a much smaller package eventually resulted in power and heat limitations. The way around this was to introduce parallelism in the processor itself, either through vector based instructions, simultaneous multi-threading or simple glue logic: just add a second independent (bar cache sharing) processor (called a “core”).] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A New Generation of Cosmic Superstring SimulationsSupercomputing with Graphics Processing Units

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Publisher
Springer International Publishing
Copyright
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023
ISBN
978-3-031-20228-5
Pages
47 –98
DOI
10.1007/978-3-031-20229-2_3
Publisher site
See Chapter on Publisher Site

Abstract

[For well over a decade, the empirical Moore’s law (a doubling in transistor count should occur every 18-24 months, courtesy of refined manufacturing processes) has been upheld. Up until the early 2000’s the way to use these extra transistors was to create more complex processors, larger caches and much faster clock frequencies. However, this eventually proved unfeasible: simply increasing clock frequencies in a much smaller package eventually resulted in power and heat limitations. The way around this was to introduce parallelism in the processor itself, either through vector based instructions, simultaneous multi-threading or simple glue logic: just add a second independent (bar cache sharing) processor (called a “core”).]

Published: Jan 14, 2023

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