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A Practical Approach to VLSI System on Chip (SoC) DesignSOC Design for Testability (DFT)

A Practical Approach to VLSI System on Chip (SoC) Design: SOC Design for Testability (DFT) [This chapter describes requirement for testability, the design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC design in the context of DFT. This chapter introduces the concept of compression and need for test optimization to reduce ATE test times and its impact on economics of SOC.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Approach to VLSI System on Chip (SoC) DesignSOC Design for Testability (DFT)

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2020
ISBN
978-3-030-23048-7
Pages
117 –139
DOI
10.1007/978-3-030-23049-4_7
Publisher site
See Chapter on Publisher Site

Abstract

[This chapter describes requirement for testability, the design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC design in the context of DFT. This chapter introduces the concept of compression and need for test optimization to reduce ATE test times and its impact on economics of SOC.]

Published: Sep 26, 2019

Keywords: DFT mode; LBIST; PMBIST; Boundary scan; JTAG; IEEE 1149.1/6; ATPG; MISR; PRPG; Scan compression

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