Get 20M+ Full-Text Papers For Less Than $1.50/day. Start a 14-Day Trial for You or Your Team.

Learn More →

A Practical Approach to VLSI System on Chip (SoC) DesignSoC Physical Design Verification

A Practical Approach to VLSI System on Chip (SoC) Design: SoC Physical Design Verification [This chapter deals with the physical design verification and design signoff procedures of a SOC design. The topics covered in detail are all steps relevant to verification of SOC designs and signoff before taping out the designs for fabrication. It also deals with the design for manufacturability (DFM), DRC, LEC, and timing checks carried out during design signoff.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Approach to VLSI System on Chip (SoC) DesignSoC Physical Design Verification

Download PDF
15 pages

Loading next page...
 
/lp/springer-journals/a-practical-approach-to-vlsi-system-on-chip-soc-design-soc-physical-Gv7Ow44UmU
Publisher
Springer International Publishing
Copyright
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
ISBN
978-3-031-18362-1
Pages
199 –214
DOI
10.1007/978-3-031-18363-8_9
Publisher site
See Chapter on Publisher Site

Abstract

[This chapter deals with the physical design verification and design signoff procedures of a SOC design. The topics covered in detail are all steps relevant to verification of SOC designs and signoff before taping out the designs for fabrication. It also deals with the design for manufacturability (DFM), DRC, LEC, and timing checks carried out during design signoff.]

Published: Dec 14, 2022

Keywords: Logic equivalence check (LEC); Physical design; Place and route; CTS; GDS II; LEF; Layout; Clock route; Power route; Detail route; DRC; LVS; ERC; Parasitic extraction; Back annotation; Floor plan; ECO

There are no references for this article.