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A Practical Approach to VLSI System on Chip (SoC) DesignStatic Timing Analysis (STA)

A Practical Approach to VLSI System on Chip (SoC) Design: Static Timing Analysis (STA) [This chapter explain the timing analysis techniques, tools for timing analysis, concept of design corners, challenges of on-chip variations in advanced technology nodes, and a few tips to address those challenges for achieving SOC timing closure.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Approach to VLSI System on Chip (SoC) DesignStatic Timing Analysis (STA)

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References (1)

Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2020
ISBN
978-3-030-23048-7
Pages
99 –116
DOI
10.1007/978-3-030-23049-4_6
Publisher site
See Chapter on Publisher Site

Abstract

[This chapter explain the timing analysis techniques, tools for timing analysis, concept of design corners, challenges of on-chip variations in advanced technology nodes, and a few tips to address those challenges for achieving SOC timing closure.]

Published: Sep 26, 2019

Keywords: Static timing analysis; STA; Constraints; SDC; SDF format; Timing violations; Slack; Design corners; Dynamic timing analysis

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