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A Practical Approach to VLSI System on Chip (SoC) DesignSynthesis and Static Timing Analysis (STA)

A Practical Approach to VLSI System on Chip (SoC) Design: Synthesis and Static Timing Analysis (STA) [This chapter has two parts. Part 1 deals with the synthesis of SOC design. It details the strategies adopted for the synthesis of different constituent designs of SOC. It also deals with the selection of a technology library, design constraints, and some useful guidelines to achieve the desired PPA goals for design. Part 2 deals with the timing verification techniques, static timing analysis, design corners, challenges of on-chip variations, and a few tips to address those challenges.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Approach to VLSI System on Chip (SoC) DesignSynthesis and Static Timing Analysis (STA)

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Publisher
Springer International Publishing
Copyright
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
ISBN
978-3-031-18362-1
Pages
79 –111
DOI
10.1007/978-3-031-18363-8_5
Publisher site
See Chapter on Publisher Site

Abstract

[This chapter has two parts. Part 1 deals with the synthesis of SOC design. It details the strategies adopted for the synthesis of different constituent designs of SOC. It also deals with the selection of a technology library, design constraints, and some useful guidelines to achieve the desired PPA goals for design. Part 2 deals with the timing verification techniques, static timing analysis, design corners, challenges of on-chip variations, and a few tips to address those challenges.]

Published: Dec 14, 2022

Keywords: Static timing analysis; STA; Technology library; Standard cell; Macros; Memories; Constraints; SDC; LINT; Synthesis; Netlist; Lib file; SDF format; Timing violations; Slack

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