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A Practical Guide for SystemVerilog AssertionsAssertion Based Verification

A Practical Guide for SystemVerilog Assertions: Assertion Based Verification Chapter 0 Use of assertions justified The growing complexity and size of digital designs have made functional verification a huge challenge. In the last decade several new technologies have emerged in the area of verification and some of them have captured their place as a requirement in the verification process. Figure 0-1 shows a block diagram of a verification environment that is adopted by a vast majority of verification teams. There are two significant pieces of technology that are used by almost all verification engineers: 1. A constrained random testbench 2. Code coverage tool The objective is to verify the design under test (DUT) thoroughly and make sure there are no functional bugs. While doing this, there should be a way of measuring the completeness of verification. Code coverage tools provide a first level measure on the verification completeness. The data collected during code coverage has no knowledge of the functionality of the design but provides information on the execution of the code line by line. By guaranteeing that every line of the DUT executed at least once during simulations, a certain level of confidence can be achieved and code coverage tolls can help achieve that. Last but not http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsAssertion Based Verification

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
1 –5
DOI
10.1007/0-387-26173-7_1
Publisher site
See Chapter on Publisher Site

Abstract

Chapter 0 Use of assertions justified The growing complexity and size of digital designs have made functional verification a huge challenge. In the last decade several new technologies have emerged in the area of verification and some of them have captured their place as a requirement in the verification process. Figure 0-1 shows a block diagram of a verification environment that is adopted by a vast majority of verification teams. There are two significant pieces of technology that are used by almost all verification engineers: 1. A constrained random testbench 2. Code coverage tool The objective is to verify the design under test (DUT) thoroughly and make sure there are no functional bugs. While doing this, there should be a way of measuring the completeness of verification. Code coverage tools provide a first level measure on the verification completeness. The data collected during code coverage has no knowledge of the functionality of the design but provides information on the execution of the code line by line. By guaranteeing that every line of the DUT executed at least once during simulations, a certain level of confidence can be achieved and code coverage tolls can help achieve that. Last but not

Published: Jan 1, 2005

Keywords: Functional Coverage; Design Signal; Stimulus Generation; Code Coverage; Verification Engineer

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