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A Practical Guide for SystemVerilog AssertionsChecking the Checker

A Practical Guide for SystemVerilog Assertions: Checking the Checker Chapter 7 Isolating assertion errors early Assertion based verification provides excellent potential for finding design bugs early in the verification cycle. The SVA language is defined to address ABV with powerful built-in constructs. Assertion failures are indicated to the user by default as required by the SystemVerilog 3.1a standard. It is not required to display the success of an assertion by default. The user can use the action block of an assertion to display successes. Since the number of successes can be numerous (since most assertions are evaluated on every clock edge), displaying every success by default can create huge log files depending on the number of assertions that are active during simulation, slowing down the simulation. A typical test configuration is shown in Figure 7-1. This is the same as Figure 0-2 shown in Chapter 0. Let's assume that a user executes this configuration and the simulation completes with a few assertion errors. The user should be absolutely confident that the error issued is a real design error. In other words, a user should be confident that his assertion code is correct and that the assertion failure is not a false condition. Debugging the entire design based on http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsChecking the Checker

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
285 –327
DOI
10.1007/0-387-26173-7_8
Publisher site
See Chapter on Publisher Site

Abstract

Chapter 7 Isolating assertion errors early Assertion based verification provides excellent potential for finding design bugs early in the verification cycle. The SVA language is defined to address ABV with powerful built-in constructs. Assertion failures are indicated to the user by default as required by the SystemVerilog 3.1a standard. It is not required to display the success of an assertion by default. The user can use the action block of an assertion to display successes. Since the number of successes can be numerous (since most assertions are evaluated on every clock edge), displaying every success by default can create huge log files depending on the number of assertions that are active during simulation, slowing down the simulation. A typical test configuration is shown in Figure 7-1. This is the same as Figure 0-2 shown in Chapter 0. Let's assume that a user executes this configuration and the simulation completes with a few assertion errors. The user should be absolutely confident that the error issued is a real design error. In other words, a user should be confident that his assertion code is correct and that the assertion failure is not a false condition. Debugging the entire design based on

Published: Jan 1, 2005

Keywords: Clock Cycle; Logical Relationship; Timing Relationship; Sensitive Signal; Stimulus Generation

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