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A Practical Guide for SystemVerilog AssertionsIntroduction to SVA

A Practical Guide for SystemVerilog Assertions: Introduction to SVA Chapter 1 Understanding the Syntax 1.1 What is an Assertion? An assertion is a description of a property of the design. • If a property that is being checked for in a simulation does not behave the way we expect it to, the assertion fails. • If a property that is forbidden from happening in a design happens during simulation, the assertion fails. A list of the properties can be inferred from the functional specification of a design and can be converted into assertions. These assertions can be continuously monitored during functional simulations. The same assertions can also be re-used for verifying the design using formal techniques. Assertions, also known as monitors or checkers, have been used as a form of debugging technique for a very long time in the design verification process. Traditionally, they are written in a procedural language like Verilog. They can also be written in PLI and C/C++ programs. The following code shows a simple mutually asserted condition check written in Verilog, wherein signal "a" and signal "b" cannot be high at the same time. If they are, an error message is displayed. "ifdef ma if(a & b) $display Chapter 1 {"Error:Mutually asserted check failed\n") http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsIntroduction to SVA

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
7 –88
DOI
10.1007/0-387-26173-7_2
Publisher site
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Abstract

Chapter 1 Understanding the Syntax 1.1 What is an Assertion? An assertion is a description of a property of the design. • If a property that is being checked for in a simulation does not behave the way we expect it to, the assertion fails. • If a property that is forbidden from happening in a design happens during simulation, the assertion fails. A list of the properties can be inferred from the functional specification of a design and can be converted into assertions. These assertions can be continuously monitored during functional simulations. The same assertions can also be re-used for verifying the design using formal techniques. Assertions, also known as monitors or checkers, have been used as a form of debugging technique for a very long time in the design verification process. Traditionally, they are written in a procedural language like Verilog. They can also be written in PLI and C/C++ programs. The following code shows a simple mutually asserted condition check written in Verilog, wherein signal "a" and signal "b" cannot be high at the same time. If they are, an error message is displayed. "ifdef ma if(a & b) $display Chapter 1 {"Error:Mutually asserted check failed\n")

Published: Jan 1, 2005

Keywords: Clock Cycle; Positive Edge; Real Success; Repetition Operator; Assert Statement

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