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A Practical Guide for SystemVerilog AssertionsSVA for Data Intensive Designs

A Practical Guide for SystemVerilog Assertions: SVA for Data Intensive Designs Chapter 4 In any design, there are two areas that need to be verified thoroughly: a. Is the control logic behaving correctly? - These signals control the flow of data in the design and have complex timing relationships between each other. b. Is my output data as expected? - This makes sure that the output data of the RTL matches the output of the golden model (usually written in C). This guarantees that the functionality of the optimized hardware algorithms implemented in RTL matches that of the golden model. In general, assertion based verification is very suited for checking signals that have complex timing relationships or in other words, the control logic. The declarative nature of the language makes it more suitable for temporal checking. While assertions don't add any additional value for data checking, it can still be used for writing efficient self-checking environments. 4.1 A simple multiplier check SystemVerilog assertions have the advantage of using most data types and operators that are part of the SystemVerilog language. This gives great flexibility in writing simple arithmetic checks. Example 4.1 A simple multiplier modul e au ( inpu t logic [7:0] a, b, c, 168 Chapter 4 inpu t http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsSVA for Data Intensive Designs

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
167 –190
DOI
10.1007/0-387-26173-7_5
Publisher site
See Chapter on Publisher Site

Abstract

Chapter 4 In any design, there are two areas that need to be verified thoroughly: a. Is the control logic behaving correctly? - These signals control the flow of data in the design and have complex timing relationships between each other. b. Is my output data as expected? - This makes sure that the output data of the RTL matches the output of the golden model (usually written in C). This guarantees that the functionality of the optimized hardware algorithms implemented in RTL matches that of the golden model. In general, assertion based verification is very suited for checking signals that have complex timing relationships or in other words, the control logic. The declarative nature of the language makes it more suitable for temporal checking. While assertions don't add any additional value for data checking, it can still be used for writing efficient self-checking environments. 4.1 A simple multiplier check SystemVerilog assertions have the advantage of using most data types and operators that are part of the SystemVerilog language. This gives great flexibility in writing simple arithmetic checks. Example 4.1 A simple multiplier modul e au ( inpu t logic [7:0] a, b, c, 168 Chapter 4 inpu t

Published: Jan 1, 2005

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