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A Practical Guide for SystemVerilog AssertionsSVA for Memories

A Practical Guide for SystemVerilog Assertions: SVA for Memories Chapter 5 Memory controller protocol Computers and consumer electronic devices have huge amount of memory to store multimedia application data. In the ASIC world, almost all the chips that are being designed today use embedded memory (DRAM, SRAM, ROM, etc.). As the memory access time is becoming faster and faster, it becomes very essential that the end product work with multiple memory vendors and with different timing requirements. The major bottleneck in the verification of memory controller interface is the timing of the control signals. This can be effectively done using assertions. The assertions written for a particular type of memory device can be re-used with multiple vendors just by modifying the timing parameters. This chapter discusses developing reusable SVA checkers for different types of memory devices. 5.1 Sample System - Memory controller The sample system has a CPU that interfaces with a memory controller. The CPU can read and write data to the various memories connected to the memory controller. The memory controller can interface to different type of memories such as SDRAM, DDR-SDRAM, SRAM, Flash, ROM, etc. The block diagram for the sample system is shown in Figure 5-1. 5.1.1 CPU - AHB Interface Operation The CPU http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsSVA for Memories

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
191 –232
DOI
10.1007/0-387-26173-7_6
Publisher site
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Abstract

Chapter 5 Memory controller protocol Computers and consumer electronic devices have huge amount of memory to store multimedia application data. In the ASIC world, almost all the chips that are being designed today use embedded memory (DRAM, SRAM, ROM, etc.). As the memory access time is becoming faster and faster, it becomes very essential that the end product work with multiple memory vendors and with different timing requirements. The major bottleneck in the verification of memory controller interface is the timing of the control signals. This can be effectively done using assertions. The assertions written for a particular type of memory device can be re-used with multiple vendors just by modifying the timing parameters. This chapter discusses developing reusable SVA checkers for different types of memory devices. 5.1 Sample System - Memory controller The sample system has a CPU that interfaces with a memory controller. The CPU can read and write data to the various memories connected to the memory controller. The memory controller can interface to different type of memories such as SDRAM, DDR-SDRAM, SRAM, Flash, ROM, etc. The block diagram for the sample system is shown in Figure 5-1. 5.1.1 CPU - AHB Interface Operation The CPU

Published: Jan 1, 2005

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