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A Practical Guide for SystemVerilog AssertionsSVA for Protocol Interface

A Practical Guide for SystemVerilog Assertions: SVA for Protocol Interface Chapter 6 SVA checkers for a sample PCI system Compliance testing has become one of the major challenges in SOC designs. It is very common for designs to support certain standard protocols. For example, graphics applications might support a standard bus interface such as PCI/PCIX, USB or IEEE 1394 Firewire. These bus interfaces help the designs achieve higher bandwidth of data transmission and also provide a standard method to connect multiple devices. Bus protocols are complex and every device sitting on the bus should be compliant with a list of rules specific to that protocol. The verification environment built for testing these standard protocol interfaces are often re-usable since the same set of rules applies to any device that supports the specific interface. Verification engineers often develop bus interface models (BIM) of the devices that support a specific interface. The BIM need not replicate the detailed intemal functionality of the device. It just has to support the basic handshaking process that is compliant with the specific interface. This helps the verification engineer to create a sample system with the BIM and the Design Under Test (DUT). Tests can be written to create transactions between the BIM and the DUT. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsSVA for Protocol Interface

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
233 –283
DOI
10.1007/0-387-26173-7_7
Publisher site
See Chapter on Publisher Site

Abstract

Chapter 6 SVA checkers for a sample PCI system Compliance testing has become one of the major challenges in SOC designs. It is very common for designs to support certain standard protocols. For example, graphics applications might support a standard bus interface such as PCI/PCIX, USB or IEEE 1394 Firewire. These bus interfaces help the designs achieve higher bandwidth of data transmission and also provide a standard method to connect multiple devices. Bus protocols are complex and every device sitting on the bus should be compliant with a list of rules specific to that protocol. The verification environment built for testing these standard protocol interfaces are often re-usable since the same set of rules applies to any device that supports the specific interface. Verification engineers often develop bus interface models (BIM) of the devices that support a specific interface. The BIM need not replicate the detailed intemal functionality of the device. It just has to support the basic handshaking process that is compliant with the specific interface. This helps the verification engineer to create a sample system with the BIM and the Design Under Test (DUT). Tests can be written to create transactions between the BIM and the DUT.

Published: Jan 1, 2005

Keywords: Clock Cycle; Data Phase; Cover Property; Target Device; Special Cycle

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