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A Practical Guide for SystemVerilog AssertionsSVA Simulation Methodology

A Practical Guide for SystemVerilog Assertions: SVA Simulation Methodology Chapter 2 In Chapter 1, SVA language constructs were discussed in detail with examples. All examples were illustrated as relationships between two or more generic signals without any design details. In Chapter 2, a dummy system is used to present a real situation. The process of protocol extraction and assertion development will be discussed step by step. Various simulation methodologies that can significantly increase the productivity of assertion based verification will be discussed. Functional coverage and reactive testbench development will be discussed in detail. 2.1 A sample system under verification The sample system under consideration is shown in Figure 2-1. The system has 3 master devices and 2 target devices. A link is established between the master and the target devices by the mediator. At a given time, only one master can conduct a transaction and with only one target device. Any master device can conduct a transaction with any target device. The transaction can be a read or a write. The mediator contains arbiter logic that decides which master will be allowed to conduct a transaction. The arbiter uses a simple round robin technique. The mediator also contains glue logic that actually decodes the master information for the http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Guide for SystemVerilog AssertionsSVA Simulation Methodology

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Publisher
Springer US
Copyright
© Springer Science+Business Media, Inc. 2005
ISBN
978-0-387-26049-5
Pages
89 –137
DOI
10.1007/0-387-26173-7_3
Publisher site
See Chapter on Publisher Site

Abstract

Chapter 2 In Chapter 1, SVA language constructs were discussed in detail with examples. All examples were illustrated as relationships between two or more generic signals without any design details. In Chapter 2, a dummy system is used to present a real situation. The process of protocol extraction and assertion development will be discussed step by step. Various simulation methodologies that can significantly increase the productivity of assertion based verification will be discussed. Functional coverage and reactive testbench development will be discussed in detail. 2.1 A sample system under verification The sample system under consideration is shown in Figure 2-1. The system has 3 master devices and 2 target devices. A link is established between the master and the target devices by the mediator. At a given time, only one master can conduct a transaction and with only one target device. Any master device can conduct a transaction with any target device. The transaction can be a read or a write. The mediator contains arbiter logic that decides which master will be allowed to conduct a transaction. The arbiter uses a simple round robin technique. The mediator also contains glue logic that actually decodes the master information for the

Published: Jan 1, 2005

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