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A Primer on Compression in the Memory HierarchyCache/Memory Link Compression

A Primer on Compression in the Memory Hierarchy: Cache/Memory Link Compression [The exponential growth in the number of transistors per chip has led to a rapid increase in the number of cores on a microprocessor chip. However, the bandwidth across the chip boundary has not grown as quickly as either the transistor count or the core count. Cache compression can increase the effective capacity of the cache, and thus tends to reduce the number of cache misses and reduce bandwidth demand. Nonetheless, off-chip bandwidth can be a performance bottleneck in many systems. Techniques that can improve the effective off-chip bandwidth can easily translate into higher performance for memory-bound applications.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2016
ISBN
978-3-031-00623-4
Pages
45 –51
DOI
10.1007/978-3-031-01751-3_5
Publisher site
See Chapter on Publisher Site

Abstract

[The exponential growth in the number of transistors per chip has led to a rapid increase in the number of cores on a microprocessor chip. However, the bandwidth across the chip boundary has not grown as quickly as either the transistor count or the core count. Cache compression can increase the effective capacity of the cache, and thus tends to reduce the number of cache misses and reduce bandwidth demand. Nonetheless, off-chip bandwidth can be a performance bottleneck in many systems. Techniques that can improve the effective off-chip bandwidth can easily translate into higher performance for memory-bound applications.]

Published: Jan 1, 2016

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