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A Primer on Hardware PrefetchingInstruction Prefetching

A Primer on Hardware Prefetching: Instruction Prefetching [Instruction fetch stalls are detrimental to performance for workloads with large instruction working sets; when instruction supply slows down, the processor pipeline’s execution resources (no matter how abundant) will be wasted. Whereas desktop and scientific workloads often exhibit small instruction working sets, conventional server workloads and emerging cloud workloads exhibit primary instruction working sets often far beyond what upper-level caches can accommodate. With trends towards fast software development, scripting paradigms, and virtualized environments with increasing software stack depth, primary instruction working sets are also growing fast. Modern hardware instruction scheduling techniques, such as out-of-order execution, are often effective in hiding some or all of the stalls due to data accesses and other long latency instructions. However, out-of-order execution generally cannot hide instruction fetch latency. As such, instruction stalls often account for a large fraction of overall memory stalls in servers.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Primer on Hardware PrefetchingInstruction Prefetching

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2014
ISBN
978-3-031-00615-9
Pages
7 –14
DOI
10.1007/978-3-031-01743-8_2
Publisher site
See Chapter on Publisher Site

Abstract

[Instruction fetch stalls are detrimental to performance for workloads with large instruction working sets; when instruction supply slows down, the processor pipeline’s execution resources (no matter how abundant) will be wasted. Whereas desktop and scientific workloads often exhibit small instruction working sets, conventional server workloads and emerging cloud workloads exhibit primary instruction working sets often far beyond what upper-level caches can accommodate. With trends towards fast software development, scripting paradigms, and virtualized environments with increasing software stack depth, primary instruction working sets are also growing fast. Modern hardware instruction scheduling techniques, such as out-of-order execution, are often effective in hiding some or all of the stalls due to data accesses and other long latency instructions. However, out-of-order execution generally cannot hide instruction fetch latency. As such, instruction stalls often account for a large fraction of overall memory stalls in servers.]

Published: Jan 1, 2014

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