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A Primer on Memory Consistency and Cache CoherenceIntroduction to Consistency and Coherence

A Primer on Memory Consistency and Cache Coherence: Introduction to Consistency and Coherence [Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. These designs seek various goodness properties, such as high performance, low power, and low cost. Of course, it is not valuable to provide these goodness properties without first providing correctness. Correct shared memory seems intuitive at a hand-wave level, but, as this lecture will help show, there are subtle issues in even defining what it means for a shared memory system to be correct, as well as many subtle corner cases in designing a correct shared memory implementation. Moreover, these subtleties must be mastered in hardware implementations where bug fixes are expensive. Even academics should master these subtleties to make it more likely that their proposed designs will work.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Primer on Memory Consistency and Cache CoherenceIntroduction to Consistency and Coherence

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2020
ISBN
978-3-031-00636-4
Pages
1 –8
DOI
10.1007/978-3-031-01764-3_1
Publisher site
See Chapter on Publisher Site

Abstract

[Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. These designs seek various goodness properties, such as high performance, low power, and low cost. Of course, it is not valuable to provide these goodness properties without first providing correctness. Correct shared memory seems intuitive at a hand-wave level, but, as this lecture will help show, there are subtle issues in even defining what it means for a shared memory system to be correct, as well as many subtle corner cases in designing a correct shared memory implementation. Moreover, these subtleties must be mastered in hardware implementations where bug fixes are expensive. Even academics should master these subtleties to make it more likely that their proposed designs will work.]

Published: Jan 1, 2020

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