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A Primer on Memory PersistencyData Persistence

A Primer on Memory Persistency: Data Persistence [In a system with volatile hardware components (like CPU registers, processor caches, etc.), simply issuing a store operation does not guarantee that the update is durably written to PM. For instance, when a store operation is issued by the CPU, modern processors perform the update to a write-back cache. The write-back cache then lazily drains the update to PM, for example, when a cache line conflict occurs. Any subsequent failure erases the volatile write-back cache (or generally, any volatile component) and the update is lost. To prevent data loss on failure, hardware systems must guarantee that the updates reach PM.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Primer on Memory PersistencyData Persistence

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2022
ISBN
978-3-031-79193-2
Pages
13 –20
DOI
10.1007/978-3-031-79205-2_2
Publisher site
See Chapter on Publisher Site

Abstract

[In a system with volatile hardware components (like CPU registers, processor caches, etc.), simply issuing a store operation does not guarantee that the update is durably written to PM. For instance, when a store operation is issued by the CPU, modern processors perform the update to a write-back cache. The write-back cache then lazily drains the update to PM, for example, when a cache line conflict occurs. Any subsequent failure erases the volatile write-back cache (or generally, any volatile component) and the update is lost. To prevent data loss on failure, hardware systems must guarantee that the updates reach PM.]

Published: Jan 1, 2022

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