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A Primer on Memory PersistencyMemory Persistency Models

A Primer on Memory Persistency: Memory Persistency Models [PM data can survive failures due to power interruptions or program crashes. In the case of a failure, recovery code inspects the PM data, reconstructs volatile state, and resumes program execution. Recovery requires that memory operations to the PM are properly ordered. Memory consistency models [58, 59] enforce the order in which memory operations are visible in shared memory systems. They specify the allowed shared memory state and observable load values when load and store operations are performed by multiple cores to overlapping memory locations. Unfortunately, these visibility constraints do not apply to the order operations are drained to PM; consistency models do not specify constraints on when an update is sent to the memory device, only on the value that subsequent loads may return (i.e., an update may linger in a writeback cache without draining to PM). As discussed earlier in Chapter 2, write-back caches, on- chip buffers, and processor interconnects may all reorder updates as they drain to PM. However, the order that writes drain to PM determines the memory image that is available to recovery code; hence, correct recovery depends critically on reasoning about the order of the writes to PM.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Primer on Memory PersistencyMemory Persistency Models

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2022
ISBN
978-3-031-79193-2
Pages
21 –50
DOI
10.1007/978-3-031-79205-2_3
Publisher site
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Abstract

[PM data can survive failures due to power interruptions or program crashes. In the case of a failure, recovery code inspects the PM data, reconstructs volatile state, and resumes program execution. Recovery requires that memory operations to the PM are properly ordered. Memory consistency models [58, 59] enforce the order in which memory operations are visible in shared memory systems. They specify the allowed shared memory state and observable load values when load and store operations are performed by multiple cores to overlapping memory locations. Unfortunately, these visibility constraints do not apply to the order operations are drained to PM; consistency models do not specify constraints on when an update is sent to the memory device, only on the value that subsequent loads may return (i.e., an update may linger in a writeback cache without draining to PM). As discussed earlier in Chapter 2, write-back caches, on- chip buffers, and processor interconnects may all reorder updates as they drain to PM. However, the order that writes drain to PM determines the memory image that is available to recovery code; hence, correct recovery depends critically on reasoning about the order of the writes to PM.]

Published: Jan 1, 2022

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