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A Synergistic Framework for Hardware IP Privacy and Integrity ProtectionFault Attack Protection and Evaluation

A Synergistic Framework for Hardware IP Privacy and Integrity Protection: Fault Attack Protection... [Fault attacks can obstruct the normal system execution by injecting errors into the hardware. By radiating the critical circuit components with high energy particle strikes, voltage transients are created to make the circuit malfunction temporarily. In recent years, fault attacks have demonstrated a great capability of leaking the cryptographics keys, and nullifying the entire system security mechanisms. The chapter introduces two protection schemes, including a new security primitive, i.e., public physical unclonable function (PPUF), that has provable time gap between the execution and simulation (ESG) to derive security, and a new analysis framework to identify critical circuit components for general purpose processors and guide the design optimization.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Synergistic Framework for Hardware IP Privacy and Integrity ProtectionFault Attack Protection and Evaluation

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References (46)

Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2020
ISBN
978-3-030-41246-3
Pages
97 –134
DOI
10.1007/978-3-030-41247-0_4
Publisher site
See Chapter on Publisher Site

Abstract

[Fault attacks can obstruct the normal system execution by injecting errors into the hardware. By radiating the critical circuit components with high energy particle strikes, voltage transients are created to make the circuit malfunction temporarily. In recent years, fault attacks have demonstrated a great capability of leaking the cryptographics keys, and nullifying the entire system security mechanisms. The chapter introduces two protection schemes, including a new security primitive, i.e., public physical unclonable function (PPUF), that has provable time gap between the execution and simulation (ESG) to derive security, and a new analysis framework to identify critical circuit components for general purpose processors and guide the design optimization.]

Published: Apr 12, 2020

Keywords: Fault attack; PPUF; ESG; Challenge-response pair; System security evaluation; Importance sampling; Statistical attack space

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